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This brief presents a low-power, high-precision neural recording circuit for closed-loop deep brain stimulation (DBS). It adopts a switched-capacitor (SC) low-pass filter (LPF) with the double sampling technique to efficiently attenuate high-frequency noise and signal with precise cut-off frequency. To improve power efficiency, this brief proposes a multi-sampling successive approximation register (SAR) analog-to-digital converter (ADC) for quantization. It synchronously samples LPF’s output, thus maximizing LPF’s power utilization. The single-channel prototype chip was fabricated in a 180 nm CMOS process. The neural recording channel consumes $31.98~ {\mu }\mathrm {W}$ from a 1.8-V supply. The proposed 11-bit multi-sampling SAR ADC features an ENOB of 10.38 bits at a sampling rate of 20.83 kS/s. The measured input-referred noise of the neural recording channel is $1.52~ {\mu }\mathrm {V_{rms}}$ for 1 Hz–300 Hz band and $1.96~ {\mu }\mathrm {V_{rms}}$ for 300 Hz–6.5 kHz band, respectively, promising a high precision for neural recording in closed-loop DBS systems.

An interface chip for atomic sensor with highly integration using multi-voltage reference is proposed in this brief. Atomic sensors are growing fast in the direction of miniaturization and convenience, and higher demands are placed on integration and low power consumption. Atomic sensors are multi-loop feedback system, the interface circuit contains signal detection and drivers, which serve to implement temperature stabilization, vertical-cavity surface-emitting laser (VCSEL) locking, voltage controlled crystal oscillator (VCXO) regulation, and magnetic field control. Reference voltage buffer (RVB) has been proposed based on the characteristics of the atomic sensor system, which can be used for the high implementation of each driver and the digitization of the signal detection circuit, reducing the power consumption and improving integration. The proposed interface chip is fabricated in 180nm CMOS technology. Measurement results show that the signal detection circuit has a programmable gain of 30 dB to 60 dB and a bandwidth of 120 Hz to 7k Hz. The equivalent input current noise density (EICND) measurement results for the interface chip at maximum programmable gain is 1.41 pA/ $\surd $ Hz@1k Hz. The ADC achieves 75.8 dB signal-to-noise ratio (SNR) at 976.8066 Hz input sine signal while operating at sampling rate of 16 kS/s.

TEC-less bolometric imagers have the advantages of size, weight, power, and cost (SWaP-C). However, the imager’s responsivity drifts dramatically with the substrate temperature, resulting in scene dynamic range (DR) degradation. This brief presents a 120°C operating range TEC-less bolometric imager with ultra-low responsivity drift. The proposed imager’s low responsivity temperature coefficient is obtained by summing the positive and negative temperature coefficients. In the readout circuit, a poly resistor and a bolometer resistor are used in series as the feedback resistor of the pre-amplifier to accomplish the above summing. The proposed readout circuit is a low-cost improvement and hardly increases the complexity. A $12~\mu \text{m}$ pixel pitch $640\times 512$ resolution vanadium oxide (VOx) bolometric imager is implemented for verification. Measurement results show that the responsivity drift is less than 20% within the 120°C temperature range, while the drift is higher than 90% without compensation. The proposed imager’s measurement noise equivalent temperature difference (NETD) is 45 mK, demonstrating good NETD performance. The proposed imager is suitable for TEC-less wide temperature range low SWaP-C applications.

A low-power digital readout integrated circuit (DROIC) for silicon diode uncooled infrared focal plane arrays (IRFPAs) is presented. The DROIC adopts a 14-bit column-level extended-counting analog-to-digital converter (ADC) based on a cascade of a coarse continuous-time $\Sigma $ - $\Delta $ ADC and a fine single-slope ADC. While the weak detector signal is integrated, the coarse conversion is implemented by a feedback current-steering digital-to-analog converter (IDAC), which shortens the signal chain and reduces the bandwidth requirement for the op-amp, to reduce power consumption. Besides, the ramp signal of the fine conversion is generated locally by an additional column-level IDAC, which matches the coarse conversion IDAC to decrease the DNL. Also, a low-power non-uniformity calibration circuit is adopted to compensate the non-uniformity of the IRFPA and adjust the ADC’s input signal range. The DROIC with 1024 $\times $ 768 pixel array is fabricated in a $0.18~\mu \text{m}$ CMOS process. The experimental results demonstrate the DROIC consumes 109mW. The noise is 1.7LSB and the equivalent input noise voltage of the column circuit is about $2.1~\mu \text{V}$ rms. The INL and DNL are less than +6.1LSB/−4.4LSB and +0.40LSB/−0.38LSB, respectively.