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This paper presents the design and integration of a fully-integrated dual-conversion zero-IF2 CMOS transceiver for 9-band MB-OFDM UWB systems from 3.1 GHz to 8.0 GHz. The transceiver integrates all building blocks including a variable-gain wideband LNA, a single combined mixer for both RF down-conversion in RX and up-conversion in TX, a fast-settling frequency synthesizer, and IQ ADCs and DACs. Fabricated in a standard 0.18-mu m CMOS process, the receiver measures maximum S11 of -13 dB, maximum NF of 8.25 dB, in-band IIP3 of better than -13.7 dBm, and variable gain from 25.3 to 84.0 dB. IQ path gain and phase mismatches of the receiver chain are measured to be 0.8 dB and 4 degrees, respectively. The transmitter achieves a minimum output P-1 dB of -8.2 dBm, sideband rejection of better than -42.2 dBc, and LO leakage of smaller than -46.5 dBc.

The fast development of the Digital Integrated Circuit (IC) techniques has promoted the trend to process a signal in digital domain. Therefore the Analog-to-Digital Converter (ADC) becomes an essential interface between the analog world and the digital signal processing system. UWB is a wireless communication system aiming at short range and high data rate applications. In a UWB receiver, a high speed ADC with a large input signal bandwidth is required and it plays a significant role to connect the RF front-end and the Digital Baseband circuits. According to the specifications of the UWB receiver, a 6-bit 500-MS/s ADC is designed. The ADC utilizes folding and interpolating architecture, which can achieve high speed and avoid a large number of comparators. The ADC consists of a fine converter of 4-bit and a coarse converter of 2-bit. An improved pre-amplifier is introduced to suppress the offset from latter stages and allow a relatively large input swing which increases the size of one LSB and enhances the capability of the ADC to tolerate the offset error. Fabricated in 0.18-μm CMOS process and operated at 1.8-V supply, the ADC measures an SNDR of 31.9dB with a sampling frequency of 500-MS/s and a Nyquist input frequency of 250MHz. The peak INL and DNL are 0.7 LSB and 0.4 LSB, respectively. The total power consumption including both analog and digital part is 173 mW, and the chip area is 1.5*1.4 mm2. This design is successfully integrated in the single chip UWB receiver.

This paper presents a complete CMOS dual-conversion zero-IF2 transceiver for 9-band MB-OFDM UWB systems from 3.1 to 8.0 GHz. The transceiver integrates all building blocks including a variable-gain wideband LNA, a single mixer for both RF down and up conversions in RX and TX, a fast-settling frequency synthesizer, and IQ ADCs and DACs. Fabricated in a standard 0.18-mu m CMOS process, the receiver measures maximum S11 of -13dB, maximum NF of 8.25 dB, in-band IIP3 of better than -13.7 dBm, and variable gain from 25.3 to 84.0 dB. IQ path gain and phase mismatch of the receiver chain are measured to be 0.8 dB band 4 degrees respectively. The transmitter achieves a minimum output P-1dB of -8.2 dBm, sideband rejection of better than 42.2 dBc, and LO leakage of smaller than -46.5 dBc.