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The 2D electron gas (2DEG) confinement on high electron mobility transistor (HEMT) heterostructures with a thin undoped GaN channel layer on the top of a grain‐boundary‐free AlN nucleation layer is studied. This is the first time demonstration of a buffer‐free epi‐structure grown with metal–organic chemical vapor deposition with thin GaN channel thicknesses, ranging from 250 to 150 nm, without any degradation of the structural quality and 2DEG properties. The HEMTs with a gate length of 70 nm exhibit good DC characteristics with peak transconductances of 500 mS mm−1 and maximum saturated drain currents above 1 A mm−1. A thinner GaN channel layer improves 2DEG confinement because of the enhanced effectiveness of the AlN nucleation layer acting as a back‐barrier. An excellent drain‐induced barrier lowering of only 20 mV V−1 at a VDS of 25 V and an outstanding critical electric field of 0.95 MV cm−1 are demonstrated. Good large‐signal performance at 28 GHz with output power levels of 2.0 and 3.2 W mm−1 and associated power‐added efficiencies of 56% and 40% are obtained at a VDS of 15 and 25 V, respectively. These results demonstrate the potential of sub‐100 nm gate length HEMTs on a buffer‐free GaN‐on‐SiC heterostructure. [ABSTRACT FROM AUTHOR]

Electrostatic discharge (ESD) reliability simulations at circuit-level are used to develop an approach for modeling the breakdown and snapback behavior of advanced MOSFET structures. The junction and gate leakage currents due to increased tunneling in the scaled-down CMOS technologies are described, and parameter extraction procedures for the model parameters are also presented.

A dual-bit trapping device, which solves most of the problems by using a split-gate structure, inspired by the HIMOS concept is presented. The device allows a high density thanks to dual-bit/cell storage and it is easily scalable since the structure is fully self-aligned and the bit areas are physically isolated.

The report stated that the key assumption in this model is that the trap-trap distance or trap-interface distance is the dominant parameter in the conduction mechanism causing anomalous charge loss. The oxide is characterized by a single parameter, the trap density. The studies stated that failure rate calculations are possible for different oxide qualities, thicknesses and voltage. Two-trap and three-trap percolation paths can limit the failure rate.

Three-dimensional simulation was applied to model the erasing operation in a realistic flash-electrically erasable programmable read only memory cell. The model was found to consistently determine the floating-gate potential and the influence of meshing aspects in the analysis of the band-to-band tunneling-generation rate. The experimental characteristics of the erasing process of the memory cell had been reproduced using only one fitting parameter, the height of the barrier between the polycrystalline Si and SiO2.

A dual-gate Flash electrically erasable programmable read only memory cell which can store two bits with only a slight decline in the cell size with respect to the single-bit case is presented. A large number of simulations conducted show that the basic capabilities of the Flash cell, such as reading, programming and erasing can be done with a particular setting of the applied voltages.