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Space is a harsh environment, full of high-energy radiation that can cause single-event effects (SEE) in orbiting satellites. Some of these effects, such as single-event upsets and single-event functional interrupts, occur when ionizing radiation causes the logical value in a memory element to change and are detectable and correctable through various error mitigation techniques. In this thesis, we develop and implement a hardware solution to combat these SEE for deployment as an experimental module on Naval Postgraduate School Satellite 1 (NPSAT-1). Based on the relatively benign orbit of NPSAT-1, industrial-grade, commercial-off-the-shelf components that have shown tolerance to radiation were selected to keep costs low. The primary source of mitigation relies on a globally triple-modular redundant microprocessor system instantiated inside of a XILINX Kintex-7 field-programmable gate array. The system consists of an open-source microprocessor without interlocked pipeline stages (MIPS) based processor softcore, a cached memory structure capable of accessing double-data rate type three and secure digital card memories, an interface to the main satellite bus, and XILINX’s soft error mitigation softcore. The hardware was tested both in and out of the system and verified to work on the ground with faults injected. Other techniques to mitigate errors due to SEE, such as memory scrubbing, are intended to be added before launch.

The collection of signals intelligence via passive direction finding and geolocation of radio frequency signals is of great concern to the military for its contribution to the development of battlespace awareness. Basic subspace direction finding techniques provide a method of determining the direction-of-arrival (DOA) of multiple signals on an array of receivers, but they have an inherent limitation in that they are narrowband by design. The impact of various signal frequencies, bandwidths, and signal to noise ratios present in the source signals received by a sparse array using the multiple signals classification (MUSIC) subspace direction-finding algorithm are evaluated in this thesis. Additionally, two performance enhancements are presented: one that reduces the MUSIC computational load and one that provides a method of utilizing collector motion to resolve DOA ambiguities.

This report provides results of a study of the application to software-defined radios (SDR) of the Maestro 49-tile Radiation-Hard-by-Design multi-processor chip developed by Boeing Corporation for the U.S. Government using DARPA-developed radiation-hard chip technology. The heart of the pipeline SDR architecture is an implementation of single-precision floating-point pipeline FFT. The details of the software architecture to achieve the pipeline operation are presented. The performance of N-point FFTs for N = 128, 256, 512, 1024, and 2048 is reported as number of processor tiles is increased. Maximum FFT throughput achieved for a 2048-point FFT is 27 million samples per second when 20 of the 49 available tiles are used for separate FFT blocks, one tile is used for input data distribution, and one tile is used for output data collection. The performance of the complete SDR is projected based upon the FFT experiments.

Cyclic Spectrum Analysis is used to exploit the cyclostationary properties of signals and systems. Implementing such a system will require high speed arithmetic processing. Investigations into high speed arithmetic and FFT design are conducted. Integrated circuits of a 45 MHz floating point multiplier, adder, and rate-1/4 radix-4 FFT butterfly, implemented with a 20-bit word size, are presented using the Genesil Silicon Compiler., http://archive.org/details/avlsidesignofrad1094528645, Lieutenant, United States Navy, Approved for public release; distribution is unlimited.

This thesis introduces an economical way of implementing the test pattern generation for built-in test. A layout generator as well as a netlist generator are written and validated. In addition, we use the netlist generator to investigate the properties of nonprimitive polynomials., http://archive.org/details/complementarymet1094528050, Commander, Republic of China Navy, Approved for public release; distribution is unlimited.

Convolutional encoding is a Forward Error Correction (FEC) technique used in continuous one-way and real time communication links. It can provide substantial improvement in bit error rates so that small, low power, inexpensive transmitters can be used in such applications as satellites and hand-held communication devices. This thesis documents the development of a programmable convolutional encoder implemented in a Field Programmable Gate Array (FPGA) from Xilinx, Inc., called the XC3064 Logic Cell Array (LCA). The encoder is capable of coding a digital data stream with any one of 39 convolutional codes. Because the LCA is used for the hardware implementation, the design can be changed or expanded conveniently in the lab. In particularly flexible systems, several encoder designs can be stored in the system RAM, each one being downloaded into the LCA under different circumstances. The encoder has a simple microprocessor interface, a register file for storage of code parameters, a test circuit, and a maximum bit rate of about 15 Mbits/s. Special design techniques like one-hot state assignment, pipelining, and the use of redundant states are employed to tailor the hardware to the LCA architecture Other ways to improve the output bit rate are suggested. The VHSIC Hardware Description Language (VFIDL) is used to model abstract behavior and to define relationships between building blocks before the hardware implementation phase, http://archive.org/details/thedesignofprogr1094528113, Naval Air Warfare Center author (civilian), Approved for public release; distribution is unlimited.

The possibility of geolocating a Long Term Evolution (LTE) subscriber station based on the timing advance ranging parameter within the network signal internals is investigated in this thesis. The basic approach to geolocation based on radial distances from multiple base stations is outlined. Specifics of the timing parameters used during LTE network entry are examined as they relate to calculating these distances. Computer simulation is used to demonstrate expected geolocation accuracy in multiple base station networks when estimating likely locations of subscriber stations on a two-dimensional coordinate mapping system. Computer simulation is further refined to demonstrate expected geolocation accuracy in multiple base station networks when estimating likely locations of subscriber stations on a three-dimensional coordinate mapping scheme. The possibility of fixes with ten times greater accuracy than in previous results in literature are shown by applying timing advance techniques to Global System for Mobile communications networks when using a two-dimensional coordinate mapping scheme. Accuracy capable of being within 50 centimeters when using a three-dimensional coordinate mapping scheme, comparable to the accuracy in Global Positioning System technologies, also is shown., http://archive.org/details/geolocationoflte109455058, US Navy (USN) author, Approved for public release; distribution is unlimited.

A logical function f is AND bi-decomposable if it can be written as f x1, x2)= h1 (x1) h2(x2), where x1 and x2 are disjoint. Such functions are important because they can be efficiently implemented. Also many benchmark functions are AND bi-decomposable. Surprisingly, the minimal sum of products (MSOP) of f is not always obtainable by finding the MSOP of h1 and h2 and applying the law of distributivity. However, a special class of functions called orthodox functions, introduced by Sasao and Butler [1], do have this property. This thesis focuses on orthodox functions, and the remaining non-orthodox functions. It is shown how to build up orthodox functions from orthodox functions on fewer variables. An algorithm is presented for generating families of non-orthodox functions. A test program is developed to test the results of the proposed algorithm and also other programs are developed to conduct experiments with both orthodox and non-orthodox functions. Results are presented that represent the first steps toward completely characterizing bi-decomposable functions that can be efficiently implemented., http://archive.org/details/minimizationofso109456005, Lieutenant Junior Grade, Turkish Navy, Approved for public release; distribution is unlimited.

The first purpose of this thesis is to implement an efficient Cross Ambiguity Function (CAF) algorithm to compute the Time Difference of Arrival (TDOA) and Frequency Difference of Arrival (FDOA) between two sampled signals. Two CAF-related MATLAB functions were written and analyzed. One implements a βcoarseγ mode and a βfineγ mode to accurately compute the TDOA and FDOA. The second plots different views of the resulting three-dimensional CAF surface. The second purpose is to develop a program to generate geometry-specific signals. Some software packages can artificially embed constant TDOAs and FDOAs between two signals. In real-world emitter-collector geometries (one emitter and two separate collectors), however, movement of the emitter and/or collectors causes time-varying TDOAs and FDOAs. A MATLAB function was written to generate pairs of Binary-Phase-Shift-Keying signals according to user-defined signal parameters and Cartesian geometries. The resulting signal pairs have realistic TDOAs and FDOAs that vary with time according to geometry and relative motion. Several signal pairs with different geometries are generated and input into the CAF functions, and the results are compared with theoretical TDOA and FDOA calculations. Finally, signals with low signal-to-noise ratios are generated to evaluate the CAFαs ability to find Low Probability of Detection signals., http://archive.org/details/implementingcros109451617, US Navy (USN) author

With the complexity of digital systems, reliability considerations are important. In many digital systems it is desirable to con-tinuously monitor, exercise and test the system in order to determine whether the system is performing as desired. Such moni-toring may enable automatic detection of failures via periodic testing or through the use of codes and checking circuits (e.g., built-in self-testing). While any complex system requires testing to ensure satisfactory performance, satellite systems require extensive testing for two additional reasons: they operate in an environment considerably different from that in which they were built, and after launch they are inaccessible to routine maintenance and repair. Because of these unique requirements, a specific solution is required such as a self-contained, autonomous, self-testing circuit. The focus of this thesis is on the design and development of a series of Built-In Self-Tests (BISTs) for use with the Configurable Fault Tolerant Processor (CFTP). The results of this thesis are two detailed designs for a Random Access Memory (RAM) BIST and a Read-Only Memory (ROM) BIST, as well as a conceptual design for a Field Programmable Gate Array (FPGA) BIST. These designs are stored on board the CFTP and are made to operate remotely and autonomously. Together, these BISTs provide a means to monitor, exercise, and test the CFTP components and thus facilitate a reliable design., Captain, United States Marine Corps, Approved for public release; distribution is unlimited.

http://archive.org/details/designmethodolog1094523012

Digital systems implemented with high-speed transistor technologies face a variety of design challenges in an effort to keep pace with the accelerating demand for performance. As device switching frequencies climb comfortably into the gigahertz range, clock skew in digital systems threatens to limit the advantages of synchronous pipelined designs. This research investigates the limitations of clock skew on high-speed digital systems by designing and simulating an 8x8 bit synchronous, pipelined multiplier using Indium phosphide (InP), heterostructure bipolar junction (HBT) transistor technology. Fundamentals of circuit analysis and the principles of junction transistor behavior are applied to design an optimal family of logic devices using current-mode logic. All testing and simulation data is based upon results obtained from Tanner SPICE design tools. Using the building blocks of this logic family, an array multiplier is constructed and further configured into five distinct pipeline implementations. By employing a different number of pipeline stages in each implementation, the trade-offs of pipelining are illustrated and clock skew is analyzed at a variety of throughput rates. Finally, the impact of clock skew on throughput performance is quantified and summarized as a reference point for further research into asynchronous control techniques, http://archive.org/details/designofsynchron109457670, Outstanding Thesis, Major, United Spates Marine Corps, Approved for public release; distribution is unlimited.

The possibility of geolocating a Long Term Evolution (LTE) subscriber station based on the timing advance ranging parameter within the network signal internals is investigated in this thesis. The basic approach to geolocation based on radial distances from multiple base stations is outlined. Specifics of the timing parameters used during LTE network entry are examined as they relate to calculating these distances. Computer simulation is used to demonstrate expected geolocation accuracy in multiple base station networks when estimating likely locations of subscriber stations on a two-dimensional coordinate mapping system. Computer simulation is further refined to demonstrate expected geolocation accuracy in multiple base station networks when estimating likely locations of subscriber stations on a three-dimensional coordinate mapping scheme. The possibility of fixes with ten times greater accuracy than in previous results in literature are shown by applying timing advance techniques to Global System for Mobile communications networks when using a two-dimensional coordinate mapping scheme. Accuracy capable of being within 50 centimeters when using a three-dimensional coordinate mapping scheme, comparable to the accuracy in Global Positioning System technologies, also is shown.

The parameters of Low Probability of Intercept (LPI) radar signals are hard to identify by using traditional periodogram signal processing techniques. Using the Wigner Distribution (WD), this thesis examines eight types of LPI radar signals. Signal to noise ratios of 0 dB and -6dB are also investigated. The eight types LPI radar signals examined include Frequency Modulation Continuous Wave (FMCW), Frank code, P1 code, P2 code, P3 code, P4 code, COSTAS frequency hopping and Phase Shift Keying/Frequency Shift Keying (PSK/FSK) signals. Binary Phase Shift Keying (BPSK) signals although not LPI, are also examined to further illustrate the principal characteristics of the WD.

With the complexity of digital systems, reliability considerations are important. In many digital systems it is desirable to con-tinuously monitor, exercise and test the system in order to determine whether the system is performing as desired. Such moni-toring may enable automatic detection of failures via periodic testing or through the use of codes and checking circuits (e.g., built-in self-testing). While any complex system requires testing to ensure satisfactory performance, satellite systems require extensive testing for two additional reasons: they operate in an environment considerably different from that in which they were built, and after launch they are inaccessible to routine maintenance and repair. Because of these unique requirements, a specific solution is required such as a self-contained, autonomous, self-testing circuit. The focus of this thesis is on the design and development of a series of Built-In Self-Tests (BISTs) for use with the Configurable Fault Tolerant Processor (CFTP). The results of this thesis are two detailed designs for a Random Access Memory (RAM) BIST and a Read-Only Memory (ROM) BIST, as well as a conceptual design for a Field Programmable Gate Array (FPGA) BIST. These designs are stored on board the CFTP and are made to operate remotely and autonomously. Together, these BISTs provide a means to monitor, exercise, and test the CFTP components and thus facilitate a reliable design.

Without the protection of atmosphere, space systems have to mitigate radiation effects. Several different technologies are used to deal with different radiation effects in order to keep the space device work properly. One of the radiation effects called Single Event Upset (SEU) can change the state of a component or data on the bus. A single error is possible to cause a system failure if it is not corrected. Besides error correction, a space system also needs the flexibility to be modified or upgraded easily. Consequently, the idea of having a TMR design instantiated in an FPGA to construct a Configurable Fault-Tolerant Processor (CFTP) developed. The TMR, which runs one program in three identical soft-core processors with voters, is a scheme used to mitigate an SEU. The full design of TMR running in an FPGA functions as a System-On-a-Chip (SOC). Both soft-core processor and FPGA offer the CFTP a great flexibility to be reconfigured. A complete TMR design includes some fundamental components besides processors and voters such as the Reconiler, Interrupt, and Error Syndrome Storage Device (ESSD). These components have their unique function in the TMR design. They are created and simulated. Factors that affect test bench-settings like processor pipelining are important to always keep in mind. A component is designed to implement proper functions first. Then it is revised to work with the processor and memory. The full design for the TMR in this thesis proves its ability to detect and correct an SEU. The follow-on research suggested is to improve the efficiency and performance of this design.

Low Probability of Intercept (LPI) radars are a class of radar systems that possess certain performance characteristics causing them to be nearly undetectable by most modern digital intercept receivers. Consequently, LPI radar systems can oper-ate undetected until the intercept receiver is much closer than the radar.s target detector. The enemy is thus faced with a sig-nificant problem. To detect these types of radar, new direct digital receivers that use sophisticated signal processing are required. This thesis describes a novel signal processing architecture, and shows simulation results for a number of LPI wave-forms. The LPI signal detection receiver is based on Quadrature Mirror Filter Bank (QMFB) Tree processing and orthogonal wavelet techniques to decompose the input waveform into components representing the signal energy in rectangular .tiles. in the time-frequency plane. By analyzing the outputs at different layers of the tree it is possible to do feature extraction, identify and classify the LPI waveform parameters, and distinguish among the various LPI signal modulations. Waveforms used as input signals to the detection algorithm include Frequency Modulated Continuous Wave, Polyphase Codes, Costas Codes and Frequency Shift Keying/Phase Shift Keying waveforms. The output matrices resulting from the most relevant layers of the QMFB tree processing are examined and the LPI modulation parameters are extracted under various signal-to-noise ratios.

A logical function f is AND bi-decomposable if it can be written as f x1, x2)= h1 (x1) h2(x2), where x1 and x2 are disjoint. Such functions are important because they can be efficiently implemented. Also many benchmark functions are AND bi-decomposable. Surprisingly, the minimal sum of products (MSOP) of f is not always obtainable by finding the MSOP of h1 and h2 and applying the law of distributivity. However, a special class of functions called orthodox functions, introduced by Sasao and Butler [1], do have this property. This thesis focuses on orthodox functions, and the remaining non-orthodox functions. It is shown how to build up orthodox functions from orthodox functions on fewer variables. An algorithm is presented for generating families of non-orthodox functions. A test program is developed to test the results of the proposed algorithm and also other programs are developed to conduct experiments with both orthodox and non-orthodox functions. Results are presented that represent the first steps toward completely characterizing bi-decomposable functions that can be efficiently implemented.

The first purpose of this thesis is to implement an efficient Cross Ambiguity Function (CAF) algorithm to compute the Time Difference of Arrival (TDOA) and Frequency Difference of Arrival (FDOA) between two sampled signals. Two CAF-related MATLAB functions were written and analyzed. One implements a βcoarseγ mode and a βfineγ mode to accurately compute the TDOA and FDOA. The second plots different views of the resulting three-dimensional CAF surface. The second purpose is to develop a program to generate geometry-specific signals. Some software packages can artificially embed constant TDOAs and FDOAs between two signals. In real-world emitter-collector geometries (one emitter and two separate collectors), however, movement of the emitter and/or collectors causes time-varying TDOAs and FDOAs. A MATLAB function was written to generate pairs of Binary-Phase-Shift-Keying signals according to user-defined signal parameters and Cartesian geometries. The resulting signal pairs have realistic TDOAs and FDOAs that vary with time according to geometry and relative motion. Several signal pairs with different geometries are generated and input into the CAF functions, and the results are compared with theoretical TDOA and FDOA calculations. Finally, signals with low signal-to-noise ratios are generated to evaluate the CAFαs ability to find Low Probability of Detection signals.

Synchronous techniques have dominated digital logic system design for decades because they are well understood and less complicated to implement. With the advent of more exotic high-speed transistors, the issues of clock skew, system performance, power consumption, and technology migration become critical to synchronous system designers. Asynchronous digital design techniques utilize a local completion signal or request(acknowledge handshake to lend the stability afforded by the global clock in synchronous systems. This research evaluates a moderately complex digital system, an 8x8-bit multiplier utilizing high speed Indium Phosphide heterostructure bipolar junction transistors, to determine whether asynchronous logic design can compete with synchronous design in terms of system speed and power consumption. Theoretical timing equations are developed that relate the relative merits of each technique for input-to- output latency and system throughput. Tanner SPICE simulation tools are used to evaluate the full 8x8-bit asynchronous array multiplier. Finally, direct comparisons are made between five separate pipelined configurations of the multiplier utilizing both synchronous and asynchronous timing methodologies. As integrated circuits become smaller, faster, and more complex, asynchronous schemes will continue to mature and become more prevalent in digital system design.

This thesis is part of an effort by the Department of Electrical and Computer (ECE) Engineering to implement distributed learning to better serve its students. Distributed learning is especially useful for a modem technologically- oriented military, which is geographically distributed. The goal of this thesis is to develop a prototype web-based course, specifically, EC2820 - Digital Logic Design. A primary sub-goal is to quantify time required and to understand the tradeoffs involved. A secondary sub-goal is to evaluate web page tools

Digital systems implemented with high-speed transistor technologies face a variety of design challenges in an effort to keep pace with the accelerating demand for performance. As device switching frequencies climb comfortably into the gigahertz range, clock skew in digital systems threatens to limit the advantages of synchronous pipelined designs. This research investigates the limitations of clock skew on high-speed digital systems by designing and simulating an 8x8 bit synchronous, pipelined multiplier using Indium phosphide (InP), heterostructure bipolar junction (HBT) transistor technology. Fundamentals of circuit analysis and the principles of junction transistor behavior are applied to design an optimal family of logic devices using current-mode logic. All testing and simulation data is based upon results obtained from Tanner SPICE design tools. Using the building blocks of this logic family, an array multiplier is constructed and further configured into five distinct pipeline implementations. By employing a different number of pipeline stages in each implementation, the trade-offs of pipelining are illustrated and clock skew is analyzed at a variety of throughput rates. Finally, the impact of clock skew on throughput performance is quantified and summarized as a reference point for further research into asynchronous control techniques

This report contains summaries of research projects in the Department of Electrical and Computer Engineering. A list of recent publications is also included which consists of conference presentations and publications, books, contributions to books, published journal papers, technical reports, and thesis abstracts.

The thesis surveys current software tools to design satellites and develops an integrated spreadsheet-based tool for preliminary spacecraft design. First, several existing and future design tools - both commercially available and company proprietary are discussed and evaluated. Second, a spreadsheet-based design tool which is generally applicable to any earth-orbiting satellite is developed. Preliminary design of all satellite subsystems is performed on separate sheets of the Excel workbook. Based on user-entered orbital data, propellant and mass budgets are also calculated. The design technique and spreadsheet implementation is presented along with the underlying "first principles" theory and equations.

Advanced techniques have been employed for decades in the location of emitted communications signals. The use of cyclostationary maximum-likelihood estimators (MLE) applied to time different of arrival (TDOA) and frequency difference of arrival (FDOA) techniques for target emitter location is a newly developed approach. This dissertation provides an introduction to traditional TDOA and FDOA methods and the underlying cyclostationary theory of pseudo-random signals. A survey of current cyclostationary TDOA and FDOA methods, the description of new maximum likelihood estimators (MLEs) and descriptions of Monte Carlo simulations follow this. By comparing performance results to those of the Complex Ambiguity Function (CAF), it is shown that the new MLE(s) outperform the CAF in nearly all cases. Also, by comparison to the Cramer-Rao lower bound, the new MLE(s) provide a hint of the ultimate power of cyclostationary techniques over stationary techniques, exceeding this stationary theoretical lower bound on performance in many cases. Finally, the new MLE(s) perform comparably in the measurement of TDOA to those cyclostationary algorithms previously derived, when adjustments are made for the different signal environments used in the heritage work.

This report contains summaries of research projects in the Department of Electrical and Computer Engineering. A list of recent publications is also included which consists of conference presentations and publications, books, contributions to books, published journal papers, technical reports, and thesis abstracts.

This report contains 55 summaries of research projects in the Department of Electrical and Computer Engineering which were carried out under funding of the Naval Postgraduate School Research Program. A list of recent publications is also included which consists of conference presentations and publications, books, contributions to books, published journal papers, and technical reports.

This work describes a scaleable, high performance, pipelined, vector processor architecture. Special emphasis is placed on performing fast Fourier transforms with mixed-radix butterfly operations. The initial motivation for the architecture was the computation of cyclostationary algorithms. However, the resulting architecture is capable of general purpose vector processing as well. A major factor affecting the performance of the architecture is the memory system design. The use of pipelining techniques, coupled with vector processing, places a substantial burden on the memory system performance. The memory design is based on an interleaved memory philosophy with a buffering technique referred to as split transaction memory (STM). A crucial aspect of the memory design is the memory decoding scheme. A design methodology is described for the specification of permutation matrices that yield near optimal performance for the memory system. Another important aspect of this work is the development of a software based simulator that allows a STM to be specified. The simulator, operating at the register transfer level, emulates the processing of an address stream by STM and records the events for post-processing. The STM simulator was used to evaluate three types of vector processing address patterns: constant stride, constant geometry radix-r butterfly, and digit reversed. A random address pattern was also analyzed in the context of general-purpose computing. STM simulation verified the near-optimal performance of the STM.

Fundamental results developed by Wiener in the 1950's are combined with new work in the area of higher-order statistics to develop and explore a general model for nonlinear stochastic processes. The Wiener model is developed for discrete nonlin- ear systems and its orthogonality properties are analyzed to characterize its output statistics. An efficient structured procedure for computing the fc th -order statistics of the model output is formulated in both the time and frequency domains. Explicit formulas that exploit the structure of the Wiener model are given for computing the cumulants and polyspectra. A necessary condition for a discrete random process to be representable by the Wiener model is discussed. A computationally efficient pro- cedure is given for matching the model output cumulants to estimated cumulants for a given process by minimizing the squared magnitude of the error. Examples of applying this procedure to given sets of data are presented.

Convolutional encoding is a Forward Error Correction (FEC) technique used in continuous one-way and real time communication links. It can provide substantial improvement in bit error rates so that small, low power, inexpensive transmitters can be used in such applications as satellites and hand-held communication devices. This thesis documents the development of a programmable convolutional encoder implemented in a Field Programmable Gate Array (FPGA) from Xilinx, Inc., called the XC3064 Logic Cell Array (LCA). The encoder is capable of coding a digital data stream with any one of 39 convolutional codes. Because the LCA is used for the hardware implementation, the design can be changed or expanded conveniently in the lab. In particularly flexible systems, several encoder designs can be stored in the system RAM, each one being downloaded into the LCA under different circumstances. The encoder has a simple microprocessor interface, a register file for storage of code parameters, a test circuit, and a maximum bit rate of about 15 Mbits/s. Special design techniques like one-hot state assignment, pipelining, and the use of redundant states are employed to tailor the hardware to the LCA architecture Other ways to improve the output bit rate are suggested. The VHSIC Hardware Description Language (VFIDL) is used to model abstract behavior and to define relationships between building blocks before the hardware implementation phase

This thesis presents the design and layout of a Gallium Arsenide (GaAs) Dynamic Random Access Memory (DRAM array of eight four-bit words including refresh circuitry. In the last several years, there has been significant research investigating the possibilities of producing much faster, lower power and high density DRAM using GaAs. Thus far, this research has yielded success on a limited basis using special materials and fabrication techniques. This design, tested and simulated using HSPICE, supports a memory access time of approximately three nanoseconds, faster than present commercial Static Random Access Memory (SRAM). The logic circuits are designed using GaAs enhancement-mode and depletion-mode (E/ D) metal semiconductor field-effect transistors (MESFETs). Charge storage is facilitated by a single GaAs MESFET connected to a parallel plate capacitor and the required minimum time between refresh is approximately three milliseconds. Power consumption is acceptable and fabrication by Vitesse Semiconductor Corporation using the HGaAs3 process is in progress. The design techniques, power consumption and timing are discussed and demonstrated for the basic logic circuits and the memory array read, write and refresh cycles. A significant increase in DRAM memory bandwidth is gained narrowing the memory bandwidth differential between primary memory and the processor.

In direct-sequence spread-spectrum systems, successful communications require phase synchronization of the incoming pseudonoise (PN) coded waveform with a locally generated replica at the receiver. It has been previously shown that sequential PN code acquisition schemes have the potential to achieve the best performance, but they are the least analyzed because of the analytical difficulties. The acquisition time for a PN code acquisition scheme is an important parameter for system design purposes. This thesis investigates the performance of two acquisition schemes in terms of the acquisition time. A fixed sample size (FSS) test and a truncated sequential probability ratio test (TSPRT) are studied with noncoherent demodulation in a classical additive white Gaussian noise (AWGN) channel and in presence of fading. Optimal selection of desired detection and false alarm probabilities, the effects of penalty time, majority logic verification schemes and channel signal to noise ratio (SNR) mismatch problems are thoroughly studied using the flow graph technique. Our results show that the TSPRT is efficient, robust (against fading), fast and suitable for real time low cost implementations.

Cache memories, which are the level of memory between the CPU and the main memory, hold small amounts of data and instructions, and allow the CPU to access the contents in them very quickly. This significantly reduces the read access time for the CPU if the required information is available in the cache. However, caches are small and can only hold the most commonly used data and instructions required by the CPU. When information requested does not appear in the cache, a "cache miss" occurs and the CPU must fetch the required data from the main memory. The Read Protection Buffer reduces this time=costly read access by attempting to predict the possible miss address, and pre-fetch the read data.

The computational efficiency of the One Bit Spectral Correlation Algorithm is compared to other cycle spectrum analysis algorithms. A transmission bandwidth advantage is discussed. A parallel computation structure which implements the OBSCA is described and a system architecture is proposed.

Fourier transform techniques have been the favored methods in the analysis of signals and systems. One major drawback of Fourier methods is the difficulty in analyzing transient and/or non-stationary behavior. Recent advances in the field of wavelet theory show much promise in alleviating these problems. This thesis considers the realizations of the wavelet decomposition and reconstruction algorithms for the discrete case. The major discussion will involve both the one and two dimensional transforms. We also present a multiple-phase development as a second and possibly a preferable method for decomposing signals.

The concealment of information passed over a non-secure communication link lies in the complex field of cryptography. Furthermore, when absolutely no secure channel exists for the exchange of a secret key with which data in encrypted and decrypted, the remedy lies in a branch of cryptology known as public-key cryptosystem (PKS). This thesis provides an in-depth study of the public-key cryptosystem. Essential background knowledge is covered leading up to a VLSI implementation of a fast modulo exponentiator based on the sum of residues (SOR) method. Fast modulo exponentiation is vital in the most popular PKS schemes. Furthermore, since all cryptosystems make use of some form of mapping functions, a neural network - an excellent nonlinear mapping techniques - provides a viable medium upon which a possible cryptosystem can be based. In examining this possibility, this thesis presents an adaptation of the back-propagation neural network to a "pseudo" public-key arrangement. Following examination of the network, a key management system is then devised. Finally, a complete top-down block diagram of an entire cryptosystem based on the neural network of this study is proposed.

Cyclic Spectrum Analysis is used to exploit the cyclostationary properties of signals and systems. Implementing such a system will require high speed arithmetic processing. Investigations into high speed arithmetic and FFT design are conducted. Integrated circuits of a 45 MHz floating point multiplier, adder, and rate-1/4 radix-4 FFT butterfly, implemented with a 20-bit word size, are presented using the Genesil Silicon Compiler.

This thesis introduces an economical way of implementing the test pattern generation for built-in test. A layout generator as well as a netlist generator are written and validated. In addition, we use the netlist generator to investigate the properties of nonprimitive polynomials.

To implement an IIR notch filter is theoretically feasible but not technically verified or validated. Two methods often used to speed up a computation are multiprocessing and pipelining. In designing a notch filter the pipelining technique is the natural choice to speed up its processing speed. To have a rapid prototype design we may employ the silicon compiler techniques and explore numerous design variations before sending for fabrication. This paper will report the alternative pipelined design of IIR notch filters. We will present the problem, explain the methodologies used in our investigation, analyze the results, and discuss the findings. We first summarize various fixed-point designs for the pipeline building component, the multiplier-adder pair. We then present the design considerations about the system integration. Various parameters are investigated in our research: pipelined stages, timing, silicon area. Additionally, the experiences and difficulties of using timing verifiers that are built in the silicon compiler will be discussed as well.

This thesis describes the need for including design for testability in a VLSI chip design and provides information on implementing a DFT strategy using the GENESIL Silicon compiler. Two structured techniques of design for testability, Scan Design and Built-in Self Test, are discussed. Also, the methodology used to implement the residue code with GENESIL for testing the multiply-add module of a second-order Infinite Impulse Response notch filter is presented. The cost, in terms of increased hardware and decreased performance, associated with implementing the residue code is examined by comparing modulo-3 and modulo-15 checking algorithms.

Pipeline techniques have been successfully applied to speeding up processing in both general and special purpose digital computers. Application of these techniques to non-recursive filters has been suggested and is quite straightforward. Application to recursive filters has not previously been shown. In this paper, the technique for applying pipeline techniques to recursive filters is shown and the advantages and disadvantages of the technique are discussed. Using these techniques, recursive digital filters operating at hitherto impossibly high rates can be designed. (Author)

The architecture and structures used by the MacPitts silicon compiler to design integrated circuits are described, and the capabilities and limitations of the compiler are discussed. The performance of several combinational and pipeline adders designed by MacPitts and a hand-crafted pipeline adder are compared. Several different MacPitts design errors are documented. Tutorial material is presented to aid in using the MacPitts interpreter and to illustrate timing analysis of MacPitts-designed circuits using the program Crystal.

Design for Testability (DFT) is receiving major emphasis in the very large scale integration design field due to increasing circuit complexity. The utility of the silicon compiler and its value to a system designer without extensive VLSI design experience is discussed. Two major techniques for DFT, Scanpath Design and Built-in Test Design, are implemented using the Genesil silicon compiler. The basic building block, the shiftable test latch, is described in random logic block form and parallel datapath form. Linear feedback shift registers used as random vector generators and signature analyzers are used in the Built-in Test design. An Automatic Test Generation program is used to provide a measure of fault coverage for the two DFT techniques. The appendix is a brief tutorial illustrating the use of the Genesil system's shiftable test latch in its different configurations

A pipeline technique by Loomis and Sinha has been applied to the design of recursive digital filters. Recursive digital filters operating at hitherto impossibly high rates can be designed by this technique. An alternate technique by R. Gnanasekaran allows high speed implementation using the state-space structure directly. High throughput is also achieved by use of pipelined multiply-add modules. The actual hardware complexity will depend upon the number of pipeline stages. These techniques are used for the design of the I IR notch filter and finally, a comparison of the performance and complexity of these two techniques is presented.

The engineering methodology for producing a fully tested VLSI chip from a design layout is presented. A 16-bit correlator, NPS CORN88, that was previously designed, was used as a vehicle to demonstrate this methodology. The study of the design and simulation tools, MAGIC and MOSSIM II, was the focus of the design and validation process. The design was then implemented and the chip was fabricated by MOSIS. This fabricated chip was then used to develop a testing methodology for using the digital test facilities at NPS. NPS CORN88 was the first full custom VLSI chip, designed at NPS, to be tested with the NPS digital analysis system, Tektronix DAS 9100 series tester. The capabilities and limitations of these test facilities are examined within this thesis. NPS CORN88 test results are included to demonstrate the capabilities of the digital test system. A translator, MOS2DAS, was developed to convert the MOSSIM II simulation program to the input files required by the DAS 9100 device verification software, 91DVS. Finally, a tutorial for using the digital test facilities, including the DAS 9100 and associated support equipments, is included as an appendix.