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In the Internet of Things (IoT) the physical objects network is described as “things” linked to sensors, software and other technologies to connect and share information through the Internet with other devices and systems. The floods lead to large losses of life and property in several countries. However, the absence of sufficient technology results in further death and property losses as a result of flooding in developed countries. This is because of a lack of flood alert systems. The objective of this paper is to monitor the flood situation and provide a text message warning in the event of a threat. The main aim of this paper is to detect rising river water levels at a safe distance away from the railways and to allow the respective authorities to take appropriate measures by means of SMS. A sensor is a system that senses and reacts to certain physical data. The 8051 microcontrollers were produced by Intel in 1981. The microcontroller is 8-bit. It has 40 DIP pins, 4 kb of ROM stores and 128 bytes of RAM and two timers and 16 bits. It is equipped with 2 timers. There are four parallel 8-bit ports that are programmable and adjustable as necessary. The hardware device that uses GSM mobile technology for the provision of an information link with a remote network is a GSM modem or a GSM module. A float switch is a level sensor type, a fluid control system that is used inside a tank. A condenser is a tool that stores electrical energy in an electric field. It's a passive electronic feature with two terminals. A LED is a semiconductor light source that transmits light through the flowing current. Liquid Crystal Display stands for LCD. It is a thin, flat display device used in a variety of electronics. A digital electronic level shifter is a system used in the transformation of signs from one logic or voltage domain to another, also known as logic level shifter or voltage level Translation. A diode is an electronic component with a two-terminal that mainly conducts current in one direction, with low resistance and high resistance in one direction. The aim of this paper is to detect early Flood and give early warnings to Needy people.

Autonomous-driving features necessitate a fault-tolerant (FT) power-management unit in 48-V automotive applications. This article presents a monolithic single-phase closed-loop masterless FT four-to-one hybrid Dickson converter IC for high-conversion-ratio 48-V automotive multi-phase applications. The chip includes: 1) a mixed-signal droop-based valley-current ON-time quasi-fixed-frequency control, which enables masterless multi-phase operation capability; 2) single-point short-circuit fault and open-circuit fault detection and blocking of any power switches or flying capacitors; 3) an optimized high-voltage (HV) power stage with fully integrated flying-capacitor-sourced gate drivers without any external bootstrap capacitors; 4) a glitch-free cross-coupled bootstrapped HV level shifter; and 5) a dual-leg bidirectional closed-loop current-sensing circuit optimized for the hybrid Dickson topology. The design was fabricated in a 0.13- $\mu \text{m}$ 90-V automotive silicon-on-insulator (SOI) bipolar-CMOS–DMOS (BCD) process. The measured results confirm the operation over 20–60-V input, 3.3-V nominal output, 3-A maximum load, and 320-kHz effective switching frequency within the automotive-grade −40 °C–+125 °C ambient temperature. The design achieves above 90% measured efficiency at maximum conversion ratio and load at room temperature. A three-phase system is used to evaluate and confirm the fault-blocking capability and continuous power delivery upon detection of a fault.

The paper presents a class-AB flipped voltage follower (FVF) cell. In contrast to previous works in the literature, FVF cell, level shifter and folded FVF cell are merged in the proposed FVF cell to offer class-AB operation along with wide input/output voltage swing and low output resistance. In the proposed FVF cell, the level shifter increases the input/output voltage swing while the folding transistor provides an alternate path for sourcing current, which results in low output resistance. The proposed FVF cell offers wide input/output voltage swing of 0.80 V/0.67 V, high gain of 0.84, wide bandwidth of 54 MHz for the worst case load capacitance of 50 pF and low output resistance of 10 Ω. The proposed FVF cell is simulated using Cadence Virtuoso Analog Design Environment in 180 nm CMOS technology. The physical layout has been designed using Cadence Virtuoso Layout XL editor and post-layout simulation results are presented to demonstrate the performance of the proposed FVF cell. The corner analysis has also been performed to show the robustness of the proposed FVF cell.

Level shifters are the prominent interfacing circuits used in VLSI systems involving multiple supply voltages for their energy-efficient operation. The hybrid pull-up network (HPN)-based level shifter (HPLS) with an enhanced speed and energy performance is proposed in this paper that minimizes the voltage drop and current contention issue prevalent in the prior art. The HPN comprises the cross-coupled PMOS and the current mirror structure to improve the standby power performance. The proposed HPLS utilizes a split-input driver as an output stage to achieve both the area and energy efficiency. In addition, the usage of a pass transistor in the pull-down network enhances the speed performance by decreasing the rise/fall times. The performance of HPLS is verified by implementing it in CMOS 180 nm technology using Cadence tool and simulated through Spectre circuit simulator. The simulation results of the HPLS reveal 9.6 ns of delay and 66.77 fJ of energy consumption for the applied input signal of 0.4 V/1 MHz with 1.8 V high supply voltage. Further, it consumes smaller static power of 0.82 nW and occupies silicon area of 204 $$\upmu $$ m $$^{2}$$ (12 $$\upmu $$ m $$\times $$ 17 $$\upmu $$ m).

A 128-b rapid single-flux-quantum (RSFQ) Advanced Encryption Standard (AES) encryption accelerator based on bit-slice architecture is proposed for the first time. Unlike the traditional methods, the method of looking up only one 256-B table to complete the entire AES round function is proposed. The proposed method can reduce nearly 50% of the hardware cost compared to the traditional method. The simple lookup table, shift, and xor operations are used in the proposed accelerator where one 256-B table needs to be stored for lookup table operations. The RSFQ logic circuits of the proposed accelerator are designed and simulated at the logic level. It consists of 136 558 JJs based on the Open Dataset of CONNECT Cell Library for AIST ADP2. The simulation results show the proposed accelerator works correctly.

In high-frequency gate drivers, especially for wide-bandgap applications, hundreds of voltages per nanosecond noise would be generated. Therefore, the sub-ns delay level shifter with high dV/dt immunity is necessary for signal conversion among different voltage domain areas. This article presents design techniques for the sub-ns delay level shifter with ultrahigh dV/dt immunity. The propagation delay of the proposed floating level shifter is dramatically reduced by utilizing the edge detection technique. In order to further improve the performance, auxiliary pull-up circuit, promoting delay matching, and self-calibration techniques are adopted, which make the proposed level shifters more suitable for high-frequency wide-bandgap applications. The level shifter is fabricated in a 0.5 μ m bipolar CMOS DMOS (BCD) process, whose results demonstrate the final level shifter achieves zero static power consumption, a 0.024 mm2 active area, and dV/dt immunity up to 250 V/ns. The measurement results show that the sub-ns delay level shifter can be realized, and the minimum delay is only 664 ps at VSSH 25 V. Its figure of merit is just 0.044 ns/( μ m × V), which is optimal among previous level shifters. The level shifters are also simulated at the 0.18 μ m BCD process, and the propagation delay can be decreased by more than 60%.

Considering the high-voltage dc-dc buck regulator applications, a high-speed dynamic level shifter for high-side bootstrapped gate driver is presented. By introducing an instantaneous dynamic current, the propagation delay of the level shifter is reduced to 0.25 ns for the high-side switch. The dV $_{SW}/dt$ immunity and reliability are improved by a clamp circuit during the positive and negative slewing. The maximum dV $_{SW}/dt$ that the proposed circuit can tolerate is up to 18V/ns. The process variation immunity is also enhanced by optimizing the design of bias current generator. The achieved area-efficient level shifter is designed based on thin gate-oxide transistors that are widely used in high-voltage process. Experimental results show that the fabricated regulator with the proposed scheme regulates well with an 18 V input, 3.3 V output, and 2 A load current.

This paper presents a fast and power-efficient high voltage level shifter architecture capable of converting low level of input voltages into extremely high output voltage levels. The presented architecture uses single type of PMOS and NMOS transistors, operated at three times the safe operating area limit of transistors. The circuit is designed to take an input signal of 1V/0 and provides multiple output signals varying between 15, 10 and 5V/0 under the specified load condition. Circuit is designed and implemented in 110nm-BCD technology using 5V capable transistors. Post-layout simulation results demonstrate a total Energy Per Transition of 5.6pJ, a static current consumption of 180pA, and a propagation delay of 2nS for an input frequency of 100MHz.

With the demand for data processing and storage increasing rapidly, the existing CMOS-based computing system is gradually unable to meet the amplification demand because of its high-power consumption. Due to high frequency and low power consumption, superconducting rapid single-flux-quantum (RSFQ) logic circuit technology is an attractive candidate. In this paper, we propose a novel placement method based on the layer layout. We layer the gates according to the logic level, which is the length of the longest path in terms of the number of clocked gates from any primary input (PI) of the circuit to the gate. Dummy gates are inserted so that any two adjacent layers can form a bipartite graph. Then the gates of each layer are reordered to minimize the half-perimeter wirelength (HPWL). Finally, the gates of each layer are assigned vertical positions to make the edges as straight as possible. The distance between adjacent layers is determined by the number of bending points of the edges between layers. We use several superconducting RSFQ logic circuits to evaluate the effectiveness of our proposed placement method, which uses HPWL and area as evaluation metrics. The experimental results show that compared with the Simulated Annealing (SA)-based placement method, the proposed approach can reduce the total HPWL and total area by an average of 77.77% and 57.56%, respectively.

A 16-channel monopolar biphasic stimulator chip with discharge function for biomedical applications is proposed and designed. To provide monopolar biphasic stimulus currents, the positive (6V) and the negative (-6V) voltage sources are supported to generate the desired current pulses of ±3 mA. The monopolar biphasic stimulator chip was fabricated in a 0.18-μm 1.8-V/3.3-V CMOS process with the common grounded p-type substrate. The overstress and reliability issues on the low-voltage transistors in the stimulator circuits were fully overcome by circuit design. The silicon area of each single channel only occupies 0.08 mm2 and the output level of stimulus current is up to ±3 mA. By applying the discharge function, safety concern of unbalanced charge in neuro-stimulation can be dealt properly. The residual average dc current is less than 3.42 nA after discharge is activated. Moreover, this chip has also been verified with both in-vitro imitation measurement and in-vivo animal test.

Integrated circuits operating in the near/subthreshold region offer low energy consumption. However, due to the constrained voltage scalability of SRAMs, efficient power delivery is difficult to achieve. A traditional implementation would require at least two distinct voltage supplies generated by possibly two power converters. In this article, a new implementation for near/subthreshold operation is presented. The proposed implementation consists of a new “converter-free” design based on a three-level voltage stack operating at 1.8 V ± 5%. Here, the leakage current from the SRAMs in the top stack is recycled to sustain the near/subthreshold operation of the logic circuits in the two lower stacks. A test chip with the proposed voltage-stacking technique was implemented in a 28-nm low- $V{\text {th}}$ (LVT) fully depleted silicon on insulator (FDSOI) technology. The test chip is an ultralow-power advanced system-on-chip (SoC) consisting of an RISC-V core, a coarse-grained reconfigurable accelerator, and peripherals. The SoC uses a current sink and an adaptive body-bias controller for voltage regulation of the intermediate voltage rails between the stacks. The proposed system achieves up to 95% power delivery efficiency with negligible area overhead (~ 1%). The silicon measurement shows that the system energy efficiency is improved by $1.6\times $ on average , and the energy consumption is reduced by 37% on average compared to the flat implementation.

A voltage-mode transmitter (TX) with a predriver and a receiver (RX) with an energy-efficient level shifter (LS) is proposed to reduce power consumption in the heavy load of a through-silicon via (TSV) input–output (I/O) interface. An N-over-N (NN) driver with the proposed predriver reduces $\text{V}_{OH}$ drift to enhance jitter characteristics. In addition, the swing level of the transmitted signal can be lowered to 600 mV with a single supply voltage at the TX. To recover the swing level, the RX is designed with the proposed LS that can operate with a data rate of 5 Gb/s. An 8-stacked TSV is emulated in the 65 nm CMOS process, and the emulated capacitance of each stack is 100 fF. The energy efficiency is 0.166 pJ/b/pF with a pseudorandom binary sequence (PRBS)-7 at 5 Gb/s and 0.205 pJ/b/pF with a PRBS-31 at 3.5 Gb/s.

A novel charge pump with current mode control suitable to work under a very-low-voltage supply is proposed in this paper. The proposed charge pump consists of two sections. The first section is a power switches stage which consists of seven cascaded DEPMOS power switches. The second section is a low voltage stage which consists of a Low Voltage Level Shifter, Current Mode control, Follower Amplifier, Error Amplifier, Soft Start Comparator, and Skip mode & Over Voltage Comparator. The charge pump has been designed, simulated, and layout in Cadence using TSMC 130 nm SOI technology with LDMOS transistors, which have very low on-resistance. The input range of the charge pump is 2.7– 4.4 V, and it can supply up to 100 mA load current. The maximum efficiency is 90%, and the chip area is only 0.597 mm².

This brief presents a novel level-shifter circuit for high-frequency high-voltage (HV) gate-drives. The proposed level shifter (LS) is designed based on a capacitive-coupler/current mirror/ latch structure which helps to extend operation voltage of a floating supply into the negative range, achieves sub-ns and constant delay, and consumes very low power from the floating supply. Additionally, common-mode noise cancellers based on a cross-current mirror and transmission gates are also presented to enhance the dV/dt immunity of the LS against slewing of the floating ground. Implemented in 0.18 $\mu \text{m}$ HV BCD-on-SOI (bipolar-CMOS-DMOS on silicon-on-isolator) process, the post-layout simulation of the proposed design shows a delay of 680 ps, 200 V/ns of $\text{d}{V} _{\mathrm {SSF}}$ /dt slew rate immunity, It dissipates no static power and only 8.1 pJ/transition from the floating supply, improving FoM1 and FoM2 of the proposed LS by 3 times and 11.7 times compared to respective state-of-the-art works.

The level shifters (LSs) are the most significant interfacing circuits in multi-supply mixed-signal systems. This letter presents a high-speed and energy-efficient voltage level shifter with wide-range conversion from sub-threshold to I/O voltage. The proposed level shifter with split-control output driver significantly enhances the speed, energy and static power performance. The proposed LS is implemented in 0.18 $$\upmu $$ m CMOS technology, and simulation results confirm that it efficiently converts sub-threshold input voltage (240 mV) to nominal output voltage (1.8 V) without employing multi-threshold devices. The proposed LS exhibits delay of 6.43 ns and energy/transition of 38.39 fJ with significantly low switching current for 0.4 V/1 MHz input signal and 1.8 V output level.

This letter presents a periodically refreshed capacitive floating level shifter (CFLS) for applications that require a conditional switching signal. The proposed structure can generate a floating signal without additional bias voltage, and all coupling capacitors (CCs) can be simultaneously refreshed. Digital low-dropout (DLDOs) regulators are integrated to show how the leakage current from a CC affects the DLDOs that are driven by conventional and proposed CFLSs. Results are measured according to the temperature and supply voltage. With a 28-nm CMOS process, the proposed CFLS achieves a delay of 8.9 ns including the I/O buffer delay and an energy consumption of 788 fJ per cycle at V DD = 0.9 V.

We have proposed a current mirror-based level shifter (LS) with a logic error detection (CMLS-LED), which is capable of converting a near-threshold signal to a super-threshold signal. The proposed CMLS-LED resolves the current contention problem observed in the conventional cross-coupled pFET-based LS (CPLS) by using the current mirror and removes the static current in the conventional current mirror LS with adopting the feedback pFET controlled by the output node. Compared with Wilson’s current mirror-based LS (WCMLS), CMLS-LED offers an enhanced speed by avoiding the threshold voltage drop of the feedback pFET and is free from the stability issue due to an incomplete output swing. Measurement results obtained from the test chip fabricated with 14-nm finFET technology, in which CMLS-LED is implemented with WCMLS, CPLS, and Osaki’s LS, shows that the proposed CMLS-LED can widen the operating voltage range by 200 mV compared wth the CPLS, along with a speed improvement of 80%, when compared to WCMLS.

In this paper, a class-AB flipped voltage follower cell with high current driving capability is proposed. The proposed flipped voltage follower (FVF) cell offers increased current sourcing capability and large input/output voltage swing due to the use of bulk-driven and level shifter techniques, respectively. Further, it uses an additional NMOS transistor connected between output and ground terminals to increase the current sinking capability and to reduce the output resistance. The stability analysis has been performed by using Routh–Hurwitz stability criteria which confirms that the proposed FVF cell is stable. The proposed FVF cell also offers a high symmetrical slew rate. The proposed FVF cell has been simulated in Cadence virtuoso analog design environment using BSIM3v3 180 nm CMOS technology and simulation results are presented to validate the effectiveness of the proposed circuit.

The increasing number of voltage domains along with the size of the data bus requires an exponential increase in the number level shifter (LS) circuits for signal interfacing, creating an exploding in silicon area and power consumption. Higher area-efficiency can be attained by further improving the integration density of the LS circuit. In this paper, we present a multi-function ultra-low-voltage LS with re-configurable logic with embedded time-borrowing latch. The proposed circuit is implemented on CMOS 45nm technology. It is capable of converting the input voltage of 0.3 V to an output voltage of 1.8 V with an input frequency of 1 MHz. The proposed architecture has achieved a superior area efficiency with reduced transistors number of $2.4\times $ and reduced power delay product (PDP) of $4.65\times $ compared with its discrete logic block level implementation when the input voltage, output voltage, and the input frequency are 0.3 V, 1.8 V, and 1 MHz, respectively. The average propagation delay and power consumption are 52.7 ns and 34.6 nW, respectively.

The current state of the telecommunications market exhibits a high potential to absorb efficient innovations in wireless connectivity, especially those that can be applied to the Internet of Things and similar domains. Contributing in that direction, this paper describes the design and implementation of a fully differential impulse-radio ultra-wideband (IR-UWB) transmitter using pulse-amplitude modulation, with an adaptive power spectrum density (PSD). The architecture can produce up to eight differential monocycles per clock pulse at its output. The number of monocycles controls the bandwidth (thus the PSD) in the mask of IR-UWB technologies, allowing adaptation to multiple standards. The complete transmitter has four main blocks: (a) a pulse generator, comprising two pulse generating circuit groups, to modulate and create a rectangular waveform; (b) an active balun with two amplifiers, to generate differential signals; (c) a digital demultiplexer, to alternate data to the pulse generating circuit groups; (d) a binary-to-thermometer decoder, to control the amount of generated monocycles per pulse. Simulations demonstrate an output pulse amplitude of 120 mV for the high logic level and of 70 mV for the low logic level, both at a 100 MHz Pulse Repetition Frequency. This produces a mean pulse duration of 277 ps, a mean central frequency of 3.8 GHz, and a mean power consumption 6.7 mW. The transmitter takes the form of an intellectual property core in a 130 nm CMOS technology. The complete transmitter area is 0.067 mm $$^2$$ , without I/O pads. The outcomes suggest that the proposed circuit can narrow or widen the output signal bandwidth, providing adaptability to different emission requirements.

In this article methods and means of ensuring electromagnetic compatibility were considered, which can be used to reduce the effect of crosstalk between conductors on the device board. We analyzed the causes and mechanism of crosstalk, which can disrupt the correct operation of the device due to a change in the logic level of the signal on the victim conductor due to the effect of crosstalk pickup on it. The simulation of the influence of interference on the signal in the passive line was automated depending with the distance between conductors, the length of the adjacent section of conductors, and conductor materials. For the study, a logical circuit of an electronic device, in particular encoder, and a printed circuit board were built. Experiments were carried out using the following data: conductor thickness of 5, 6 and 1.2 mils, conductor spacing of 5 and 6 mils, adjacent conductor lengths of 4340. 2020, 1620, 1050, 630, 320 and 300 mils, and materials conductors that have different values of specific electrical conductivity: silver (62,500,000 S/m), copper (5950,000 S/m), platinum (10,000,000 S/m), gold (43,000,000 S/m), nickel (15,000,000 S/m), aluminum (35*106 S/m), steel (1400000 S/m). The data on the values of crosstalk were obtained. Research performed at the designed logic circuit electronic device and its circuit board. The data on the values of crosstalk were obtained according to the constructed reports. In the course of these studies, the dependences of an increase in the value of crosstalk on an increase in the length of adjacent sections, a decrease in the distance between conductors.

This brief presents a fast and energy-efficient level shifter with wide conversion range. To achieve both energy-efficient and high-speed voltage level conversion, a novel architecture combined with multi-threshold CMOS technique is employed in the proposed circuit. A mixed-threshold current mirror circuit is proposed to solve the reduced swing issue in the prior arts. Moreover, auxiliary bias circuits are inserted to guarantee that the low-threshold pull down networks could be strongly cut off while in leaking state. As a result, the power consumption would be reduced to a great extent. Measurement results based on SMIC 55-nm MTCMOS process demonstrate that the proposed level shifter could provide robust voltage conversion from 0.12V to 1.2V. At the target voltage of 0.3V, the proposed level shifter shows a propagation delay of 17.86ns, a static power of 73.95pW, and an energy per transition of 26.59fJ for input frequency of 1MHz.

We propose architectural advances in low voltage, energy-efficient, level shifters. A write assist circuit is introduced, to support the up-conversion of deep subthreshold inputs. We also present an approach to reduce the leakage current in split signal output stages. A prototype was created in a 130 nm bulk CMOS process, and some samples were successfully tested for input voltages as low as 5 mV. For 10 measured samples, the mean functional, minimum, input voltage was 31.1 mV. By applying body bias to selected NMOS transistors to compensate for process and mismatch variation, the measured mean minimum input voltage was lowered to 14.3 mV. The leakage reduction in the split control output driver reduces the driver leakage by a factor of 8. The designed level shifter was found to be energy efficient compared to published structures, it consumed an average of 25.9 fJ per conversion in post-layout simulations and the delay was measured to 21.08 ns at 300 mV input signals.

The conversion method of netlists consisting of conventional logic gates to RSFQ circuits is proposed. It treats netlists for CMOS circuits as the design entry and converts them to the netlists of RSFQ circuits, considering the reduction of the number of clocked gates, including D flip-flops (DFFs) for path balancing. It utilizes two kinds of special RSFQ gates for the reduction. One is a confluence buffer that can be utilized for realizing logic- or . The other is a small resettable DFF which can be utilized as an NIMPLY gate with the tuning of the order of pulse arrivals. The detection methods of replaceable gates with those two kinds of gates are proposed. An automatic test pattern generation tool is utilized for detecting replaceable or gates to speed up the previously proposed detection method. To minimize the number of clocked gates considering the cost of replacements, the selection problem of gates for replacements with those special RSFQ gates and the assignment of a logic level for each gate are formulated as an instance of integer linear programming. The proposed conversion method has been evaluated with ISCAS85 circuits, a 32-bit ALU, and a 64-bit ALU. The evaluation results show that the number of clocked gates and the latency in the cycles of circuits is reduced by about 10%. The delay time of the converted circuits has been estimated and the reduction of delay overhead is discussed.

To trigger events for application-specific data transfer among registers in a multimillion-gate system-on-chip (SoC), various kinds of clock signals, selectively driven by different frequency-dependent sources and/or dividers (DIVs), are usually centralized in one or more clock generation modules, where clock gating cells (CGCs), multiplexers (MUXes) and DIVs are used to create the clocks required by different functional operations in an SoC. These modules will introduce uncommon and longer timing paths for clock propagations and further make the clock tree synthesis (CTS) process become more challenging due to the on-chip-variation (OCV) effects. In addition, high volume of switching activities in the increased number of clock logic cells will consume more power. In this article, a novel design platform, merging and replacing of multiple multiplexers and dividers (MRMMD), is developed to intelligently identify those suspicious clock architectures and resynthesize them into a power-and-area effective and less complicated clock structure. Using our resynthesis platform, not only the number of clock-related timing paths and their corresponding logic levels can be reduced, but also the corresponding analysis and implementations of clock skew minimizations during CTS become much easier. The experimental results implemented in TSMC 55- and 28-nm process nodes on optimizing some industrial clock architectures showed that significant reductions of area, power, latency, skew and clock path, logic level, OCV impact, total wire length, and implementation runtime are achieved using our MRMMD platform.

In this article, a microcontroller-based high-accuracy dew-point (DP) instrument using a quartz crystal resonance (QCR) sensor is developed. The sensor is a symmetrical double cooled QCR DP sensor, which has the characteristics of efficient cooling and stable oscillation. Based on the proportional—integral—differential control method, the logic level signal and the oscillation amplitude outputted by the drive circuit are used as control feedback to obtain an optimized expert strategy control system, and the automatic DP tracking measurement is realized by the microcontroller. It is proved by experiments that the measurement error of the instrument in the range of 0–15 °C dew point (DP) environment is less than 0.3 °C DP, and it has a good performance of tracking measurement in a dynamic DP environment.

Purpose In complementary metal-oxide-semiconductor (CMOS) logic circuits, there is a direct square proportion of supply voltage on dynamic power. If the supply voltage is high, then more amount of energy will be consumed. Therefore, if a low voltage supply is used, then dynamic power will also be reduced. In a mixed signal circuit, there can be a situation when lower voltage circuitry has to drive large voltage circuitry. In such a case, P-type metal-oxide-semiconductor of high-voltage circuitry may not be switched off completely by applying a low voltage as input. Therefore, there is a need for level shifter where low-voltage and high-voltage circuits are connected. In this paper the multi-scaling voltage level shifter is presented which overcomes the contention problems and suitable for low-power applications. Design/methodology/approach The voltage level shifter circuit is essential for digital and analog circuits in the on-chip integrated circuits. The modified voltage level shifter and reported energy-efficient voltage level shifter have been optimally designed to be functional in all process voltage and temperature corners for VDDH = 5V, VDDL = 2V and the input frequency of 5 MHz. The modified voltage level shifter and reported shifter circuits are implemented using Cadence Virtuoso at 90 nm CMOS technology and the comparison is made based on speed and power consumed by the circuit. Findings The voltage level shifter circuit discussed in this paper removes the contention problem that is present in conventional voltage level shifter. Moreover, it has the capability for up and down conversion and reduced power and delay as compared to conventional voltage level shifter. The efficiency of the circuit is improved in two ways, first, the current of the pull-up device is reduced and second, the strength of the pull-down device is increased. Originality/value The modified level shifter is faster for switching low input voltage to high output voltage and also high input voltage to low output voltage. The average power consumption for the multi-scaling voltage level shifter is 259.445 µW. The power consumption is very less in this technique and it is best suitable for low-power applications.

A self-adaptive pulse generator featuring with short pulse width to realize lower power consumption and higher reliability of high voltage gate driver IC is proposed. Under the control of the feedback signal from the output of the high voltage level shifter, the pulse width of the input narrow pulse can be decreased adaptively without affecting the normal operating function. The proposed self-adaptive pulse generator is implemented in 100 V BCD process. Measured results show that the pulse width reduced from 211.6 to 108.3 ns, the high side operating current decreased from 175.54 to 120.53 µA at 25 °C when operations at 100 kHz, and the pulse width tend to be stable as temperature changes.