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We propose a new and fast method for monitoring contact hole roughness (CHR), which can be a major yield-loss factor for advanced SRAMs. The method, defect-review scanning electron microscopy (SEM) image processing, can monitor CHR 100 times faster than the conventional method by critical dimension (CD)-SEM. The speed can facilitate faster identification of process countermeasures by, for example, making detailed monitoring of CHR variation within a wafer practicable. Results for CHR obtained by both new and conventional methods show similar trends for differences in process conditions. Also, we experimentally confirmed the new method's measuring variation of the rate of deformed contact holes. Through evaluation by the new method, we demonstrate that the standby electric current of advanced SRAM depends not only on overlay error but also on CHR. We believe that the new method will be very useful in the evaluation of process countermeasures and their stability. Index Terms--Electron beams, inspection, integrated circuit manufacture, logic devices, SRAM chips.

Various studies are conducted to analyze the resonant dynamics of different nonlinear optical microdisks. The optical bus line intensity requirements are found to be highly dependent on the offset between the operating and the un-illuminated resonance wavelength.

In this paper, we present a hierarchical structure and framework for the modeling, specification, analysis and design of logic controllers for a reconfigurable machining system (RMS). This hierarchical framework allows one to integrate controllers at various levels of coordination in the machining system. Our approach is modular and "object oriented." This allows reusability and rapid reconfigurability of the controller as the machining system is reconfigured. In this paper, we utilize the concept of timed transition models (TTM) introduced by Ostroff to model a RMS. To specify the desired controlled behavior of the RMS, we use the tools of real-time temporal language introduced by Manna and Pnueli. In this framework, the controller analysis problem can be posed as the problem of verifying that certain logical formulae are valid. Such verification can be carried out using either theorem proving techniques or model checking. We present some analytical results on a problem of system reconfiguration. An iterative approach for designing a controller based on the analysis result mentioned above is also presented. Using this approach, we can design a controller for a given set of closed-loop properties which guarantees correctness of the closed-loop system. This paper also illustrates how the state explosion problem inherent in model checking can be handled effectively by performing modular verification. Index Terms--Formal verification, logic control, machining systems, reconfigurable manufacturing systems, RTTL, TTM.

A study fabricated and tested a three-dimensional, rapid single flux quantum logic circuit based on a new type of superconducting, stacked, three-terminal device called the stackron. The junctions in the study were used as active devices. The stackrons with overdamped junctions ought to increase the packaging capability and perhaps the maximum clock frequency of a rapid single flux quantum logic circuit. Experiments results are discussed.

A study designed, fabricated and characterized a simple, rapid single-flux-quantum logic circuit using a single-layer, high critical temperature, superconducting, yttrium barium copper oxide thin film structure with four bi-crystal grain boundary Josephson junctions. The circuit includes one readout and one storage superconducting quantum interference device (SQUID). Experimental design and results are presented.

The superconducting voltage-state logic family called complementary output switching logic (COSL) has been designed through a Monte Carlo optimization process. The circuits had a theoretical yield at 5 to 10 Gb/s clock speeds even in the presence of Josephson process variations. The Monte Carlo optimization strategy is presented and theoretical yields are computed for the COSL 2- and 3-bit encoder circuits. The circuit simulations employ 5-10-GHz sinusoidal clocks and measured global and local process deviations.

This paper presents the design of fuzzy logic controllers (FLC's) for nonlinear systems with guaranteed closed-loop stability and its application on combining controllers. The design is based on heuristic fuzzy rules. Although each rule in the FLC refers to a stable closed-loop subsystem, the overall system stability cannot be guaranteed when ali these rules are applied together. In this paper, it is proved that if each subsystem is stable in the sense of Lyapunov (ISL) under a common Lyapunov function, the overall system is also stable ISL. Since no fuzzy plant model is involved, the number of subsystems generated is relatively small, and the common Lyapunov function can be found more easily. To probe further, an application of this design approach to an inverted pendulum system that combines a sliding-mode controller (SMC) and a state feedback controller (SFC) is to be reported. Each rule in this FLC has an SMC or an SFC in the consequent part. The role of the FLC is to schedule the final control under different antecedents. The stability of the whole system is guaranteed by the proposed design approach. More importantly, the controller thus designed can keep the advantages and remove the disadvantages of the two conventional controllers. Index Terms - Combining controllers, fuzzy logic control, Lyapunov, stability.

A design for a single-electron logic device that uses the binary decision diagram (BBD) concept is proposed. This equipment functions as a two-way switch for single-electron transport and is composed of four tunnel junctions. The implementation of combinational logic is achieved through the connection of identical unit devices into a cascade to construct the tree of a BBD graph.

A charge injection transistor, which functions as an exclusive-OR logic gate, and a monolithic multiterminal device, electrically reprogrammable between OR and NAND logic function, were successfully devised in a Si/Si(sub 0.7)Ge(sub 0.3) heterostructure grown by rapid thermal epitaxy on a Si substrate. Microwave measurements show a short circuit current gain cutoff of 6 GHz, for a device with a source-drain distance of 0.5 micron. Device simulations were utilized to determine primary dependencies of the device performance on the parameters employed in the design of the structure.

A Josephson 5-b serial-to-parallel decoder has been applied to a crossbar by integrating a serial train of seven data bits at the input. The first five bits incorporate the code for the selection of one of the 32 output lines. The other two encode the criteria for the selected decoder in the crossbar switch to produce an output. The decoder can perform under severe current, power, and size constraints, with the optimum input address rate being 2 Gb/s. The device uses logic functions such as pulsers, XNOR gates, asymmetric superconducting quantum interference devices, and timed inverters.

Optimal designing of a chip-set, utilizing fast interconnect delays, high wire density and high pin-counts of MCM-D/flip-chip technology, increases performance/cost ratios. The MCM-D/flip-chip solder bump technology provides a fundamental design view paradigm shift, from a monolithic to a multilithic one, in the criteria of high performance silicon systems. The on-MCM interconnect is equally fast as the on-IC interconnect. Thus, raised yields from IC's come from optimal partitioning.

The characteristics of the light amplifying optical switch (LAOS) used for improving the logic functions of pixels in parallel digital procesing systems are studied. The device is composed of of a hetrojunction phototransistor vertically integrated with a light emitting diode. It exhibits strong sensitivity to a broad spectrum of input light and can be fabricated with small area mesa structures. Analysis of several logic gates using the LAOSshows that it can provide sufficient light output with negligible optical crosstalk.

A linear, noninverting unity-gain buffer with both rail-to-rail input and rail-to-rail output (RRI-RRO) features is proposed and verified through simulation. The circuit is composed of a rail-to-rail operational amplifier and two identical nonlinear circuits connected in a direct function-inverse function configuration.