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A quantum-dot cellular automata(QCA) latch is an elementary building block, which can be used to build shift registers and logic devices for clocked QCA architectures. The operation of a QCA latch and a shift register, are discussed, and the analysis and presentation of the types and properties of errors encountered in their operation are presented.

In this paper, we describe parallel dynamic logic (PDL) which exhibits high speed without charge sharing problem. PDL uses only parallel-connected transistors for fast logic evaluation and is a good candidate for high-speed low-voltage operation. It has less back-bias effect compared to other logic styles, which use stacked transistors. Furthermore, PDL needs no signal ordering or tapering. PDL with speed-enhanced skewed static logic renders straightforward logic synthesis without the usual area penalty due to logic duplication. Our experimental results on two 32-bit carry lookahead adders using 0.25-/[micro]m CMOS technology show that PDL with speed-enhanced skewed static (SSS) logic reduces the delay over clock-delayed(CD)-domino by 15%-27% and the power-delay product by 20%-37%. Index Terms--Adder, dynamic logic, low-power, skewed logic.