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One of the major challenges for process control is wafer to wafer and lot to lot variation, for the 14nm technology node and beyond. Most of advanced process control (APC) is based on product groups, and different product groups exhibit different amounts of parameter tuning. Because lithography pattern density varies between product groups, it is difficult or impossible to share APC threads between different product groups. This paper will introduce a new method to optimize current APC into a dynamic control. With dynamic control, product groups having different pattern density will have a similar amount of parameter tuning and all product groups could share APC feedback. This paper also shows the simulation results and predicts CD sigma with dynamic control.

This paper will focus on the process impact of the intentional change in the mask writing grid. Grids ranging from 1nm to 4nm (defined at mask level) were used to investigate the effect on test structures in critical locations. The impact on optical proximity correction (OPC) to control line end pull back, corner rounding and general image fidelity will be investigated on >1 numerical aperture (NA) immersion imaging system.

A study has been completed to investigate the imaging performance with the industry standard 6% attenuated phase shift mask. Several test structures were used to investigate the effects on line edge roughness (LER) based on the polarization state of the illuminator. The use of a high NA (>1NA) immersion exposure system was employed to study the imaging characteristics.

Aerial image measurement is a key technique for model based optical proximity correction (OPC) verification. Actual aerial images obtained by AIMS (aerial image measurement system) or WLCD (wafer level critical dimension) can detect printed wafer weak point structures in advance of wafer exposure and defect inspection. Normally, the potential wafer weak points are determined based on optical rule check (ORC) simulation in advance. However, the correlation to real wafer weak points is often not perfect due to the contribution of mask three dimension (M3D) effects, actual mask errors, and scanner lens effects. If the design weak points can accurately be detected in advance, it will reduce the wafer fab cost and improve cycle time. WLCD or AIMS tools are able to measure the aerial images CD and bossung curve through focus window. However, it is difficult to detect the wafer weak point in advance without defining selection criteria. In this study, wafer weak points sensitive to mask mean-to-nominal values are characterized for a process with very high MEEF (normally more than 4). Aerial image CD uses fixed threshold to detect the wafer weak points. By using WLCD through threshold and focus window, the efficiency of wafer weak point detection is also demonstrated. A novel method using contrast range evaluation is shown in the paper. Use of the slope of aerial images for more accurate detection of the wafer weak points using WLCD is also discussed. The contrast range can also be used to detect the wafer weak points in advance. Further, since the mean to nominal of the reticle contributes to the effective contrast range in a high MEEF area this work shows that control of the mask error is critical for high MEEF layers such as poly, active and metal layers. Wafer process based weak points that cannot be detected by wafer lithography CD or WLCD will be discussed.

This paper presents the details on the use of dual illumination conditions through double exposure to support the imaging of contact holes through pitch for 65nm node applications. Data generated from a 0.85 NA ArF ASML TWINSCAN(TM) system will be presented. The authors will also present simulation and process data to understand the limitations and improvements in imaging capability.

Various types of line ends have been evaluated for either straight CPL mask or hybrid type builds. The authors will focus on image line end shortening and the impact of through dose and focus performance for very high NA ArF imaging. Simulations on test structures have been calculated along with in photoresist simulations to predict the impact on process window capability. Test structures have been designed and fabricated into a functional test for evaluation. Process evaluations have been completed and exposure-defocus window calculated.

Historical data indicates reticle write times are increasing node-to-node. The cost of mask sets is increasing driven by the tighter requirements and more levels. The regular introduction of new generations of mask patterning tools with improved performance is unable to fully compensate for the increased data and complexity required. Write time is a primary metric that drives mask fabrication speed. Design (Raw data) is only the first step in the process and many interactions between mask and wafer technology such as OPC used, OPC efficiency for writers, fracture engines, and actual field size used drive total write time. Yield, technology, and inspection rules drive the remaining raw cycle time. Yield can be even more critical for speed of delivery as it drives re-writes and wasted time. While intrinsic process yield is important, repair capability is the reason mask delivery is still able to deliver 100% good reticles to the fab. Advanced nodes utilizing several layers of multiple patterning may require mask writer tool dedication to meet image placement specifications. This will increase the effective mask cycle time for a layer mask set and drive the need for additional mask write capability in order to deliver masks at the rate required by the wafer fab production schedules.

Reticle critical dimension uniformity (CDU) is one of the major sources of wafer CD variations which include both inter-field variations and intra-field variations. Generally, wafer critical dimension (CD) measurement sample size interfield is much less than intra-field. Intra-field CDU correction requires time-consumption of metrology. In order to improve wafer intra-field CDU, several methods can be applied such as intra-field dose correction to improve wafer intra-field CDU. Corrections can be based on CD(SEM) or aerial image metrology data from the reticle. Reticle CDU and wafer CDU maps are based on scanning electron microscope (SEM) metrology, while reticle inspection intensity mapping (NuFLare 6000) and wafer level critical dimension (WLCD) utilize aerial images or optical techniques. Reticle inspecton tools such as those from KLA and NuFlare, offer the ability to collect optical measurement data to produce an optical CDU map. WLCD of Zeiss has the advantage of using the same illumination condition as the scanner to measure the aerial images or optical CD. In this study, the intra-field wafer CDU map correlation between SEMs and aerial images are characterized. The layout of metrology structures is very important for the correlation between wafer intra-field CDU, measured by SEM, and the CDU determined by aerial images. The selection of metrology structures effects on the correlation to SEM CD to wafer is also demonstrated. Both reticle CDU, intensity CDU and WLCD are candidates for intra-field wafer CDU characterization and the advantages and limitations of each approach are discussed.

A robust optical proximity correction (OPC) model must include process variation to be effective in volume manufacturing. Often, calibration of an OPC model is based on data from a single scanner. However, scanner and mask three dimension (3D) effects have been found to affect printing performance and OPC model effectiveness [1]. OPC model robustness is improved if the fingerprints of different scanners are matched as closely as possible. Scanner source map or boundary condition variations can cause isolated and dense feature focus differences between different scanners. The scanner used to build a robust OPC model should have a minimum focus difference between isolated and dense features. Mask 3D effects must be included in OPC model building. Even if the design data is the same, mask 3D effects will vary by different advanced blank film stacks and model fitting will lead to different results. In this work, the effects of focus differences between nested and isolated features for OPC model building are quantified. In addition, mask 3D effect contributions to OPC models will also be illustrated. OPC model tolerance to variation is shown using data from multiple scanners and mask topographies and methodologies to optimize OPC models are presented. The data confirms that different absorber thickness, and n and k values, for advanced binary masks will influence the boundary conditions and effect lithographic performance. A thinner absorber demonstrated better CD prediction than thicker blanks in semi-dense and isolated patterns for both CDTP and inverse CDTP. It also shows that the thinner absorber has better inverse linearity in small isolated features, and has much better prediction for large isolated patterns. The generation of OPC models must include variations due to mask material properties and scanner optical variations to provide robust performance in manufacturing.

Traditional methods of making tool selections for semiconductor manufacturing facilities tend to focus on minimizing equipment capital costs or minimizing wafer costs. A model that comprehends the effects of tool performance, product specifications, processing costs, and die yield to analyze alternate tooling strategies for lithography exposure equipment has been developed. This model enables the investigation of the profit implications of a given tool strategy. The economic framework for this model is reviewed, as are the inputs required for the lithography-specific implementation. Generalized specifications are developed for some generic I-line and DUV tools, and a process flow is defined for a generic logic device. The model is then applied using two types of analysis. The first application quantifies the differences in fab costs for several altermate tool selections. The second application investigates several multi-year tooling strategies.

A survey supported by SEMATECH and administered by David Powell Consulting was sent to semiconductor industry leaders to gather information about the mask industry as an objective assessment of its overall condition. The survey was designed with the input of semiconductor company mask technologists and merchant mask suppliers. 2012 marks the 11 th consecutive year for the mask industry survey. This year’s survey and reportin g structure are similar to those of the previous years with minor modifications based on feedback from past years and the need to collect additional data on key topics. Categories include general mask information, mask processing, data and write time, yield and yield loss, delivery times, and maintenance and returns. Within each cate gory are multiple questions that result in a detailed profile of both the business and technical status of the mask industry. Results, initial observations, and key comparisons between the 2011 and 2012 survey responses are shown here, including multiple indications of a shift towards the manufacturing of higher end photomasks. Keywords: Mask industry, photomask, mask yield, photomask yield, mask quality, photomask quality

With each new generation of e-beam mask writers comes the ability to write leading edge photomasks with improved patterning performance and increased throughput. However, these cutting-edge e-beam tools are often used with older generation resists, preventing the end-user from taking full advantage of the tool’s potential. The generation gap between tool and resist will become even more apparent with the commercialization of multi-beam mask writers, which are expected to be available for pilot line use around 2015. The mask industry needs resists capable of meeting the resolution, roughness, and sensitivity requirements of these advanced tools and applications. The E-beam Resist Test Facility (ERTF) has been established to fill the need for consortium-based testing of e-beam resists for mask writing applications on advanced mask writers out to the 11nm half-pitch node and beyond. SEMATECH and the College of Nanoscale Science and Engineering (CNSE) began establishing the ERTF in early 2012 to test e-beam resist samples from commercial suppliers and university labs against the required performance metrics for each application at the target node. Operations officially began on June 12, 2012, at which time the first e-beam resist samples were tested. The ERTF uses the process and metrology infrastructure available at CNSE, including a Vistec VB300 Vectorscan e-beam tool adjusted to operate at 50kv. Initial testing results show that multiple resists already meet, or are close to meeting, the resolution requirements for mask writing at the 11nm node, but other metrics such as line width roughness still need improvement. An overview of the ERTF and its capabilities is provided here. Tools, baseline processes, and operation strategy details are discussed, and resist testing and benchmarking results are shown. The long-term outlook for the ERTF and plans to expand capability and testing capacity, including resist testing for e-beam direct write lithography, are also discussed.

The semiconductor industry is under constant pressure to reduce production costs even as the complexity of technology increases. Lithography represents the most expensive process due to its high capital equipment costs and the implementation of low-k1 lithographic processes, which have added to the complexity of making masks because of the greater use of optical proximity correction, pixelated masks, and double or triple patterning. Each of these mask technologies allows the production of semiconductors at future nodes while extending the utility of current immersion tools. Low-k1 patterning complexity combined with increased data due to smaller feature sizes is driving extremely long mask write times. While a majority of the industry is willing to accept times of up to 24 hours, evidence suggests that the write times for many masks at the 22 nm node and beyond will be significantly longer. It has been estimated that funding on the order of $50M to $90M for non-recurring engineering (NRE) costs will be required to develop a multiple beam mask writer system, yet the business case to recover this kind of investment is not strong. Moreover, funding such a development poses a high risk for an individual supplier. The structure of the mask fabrication marketplace separates the mask writer equipment customer (the mask supplier) from the final customer (wafer manufacturer) that will be most effected by the increase in mask cost that will result if a high speed mask writer is not available. Since no individual company will likely risk entering this market, some type of industry-wide funding model will be needed.

Defectivity has been historically identified as a leading technical roadblock to the implementation of nanoimprint lithography for semiconductor high volume manufacturing. The lack of confidence in nanoimprint's ability to meet defect requirements originates in part from the industry's past experiences with 1 × lithography and the shortage in enduser generated defect data. SEMATECH has therefore initiated a defect assessment aimed at addressing these concerns. The goal is to determine whether nanoimprint, specifically Jet and Flash Imprint Lithography from Molecular Imprints, is capable of meeting semiconductor industry defect requirements. At this time, several cycles of learning have been completed in SEMATECH's defect assessment, with promising results. J-FIL process random defectivity of < 0.1 def/cm2 has been demonstrated using a 120nm half-pitch template, providing proof of concept that a low defect nanoimprint process is possible. Template defectivity has also improved significantly as shown by a pre-production grade template at 80nm pitch. Cycles of learning continue on feature sizes down to 22nm. © 2011 SPIE.

The semiconductor industry is under constant pressure to reduce production costs even as technology complexity increases. Lithography represents the most expensive process due to its high capital equipment costs and the implementation of low-k1 lithographic processes, which has added to the complexity of making masks through the greater use of optical proximity correction, pixelated masks, and double or triple patterning. Each of these mask technologies allows the production of semiconductors at future nodes while extending the utility of current immersion tools. Low k1 patterning complexity combined with increased data due to smaller feature sizes is driving extremely long mask write times. While a majority of the industry is willing to accept mask write times of up to 24 hours, evidence suggests that the write times for many masks at the 22 nm node and beyond will be significantly longer. It has been estimated that $50M+ in non-recurring engineering (NRE) costs will be required to develop a multiple beam mask writer system, yet the business case to recover this kind of investment is not strong. Moreover, funding such a development is a high risk for an individual supplier. The problem is compounded by a disconnect between the tool customer (the mask supplier) and the final mask customer that will bear the increased costs if a high speed writer is not available. Since no individual company will likely risk entering this market, some type of industry-wide funding model will be needed. Because SEMATECH's member companies strongly support a multiple beam technology for mask writers to reduce the write time and cost of 193 nm and EUV masks, SEMATECH plans to pursue an advanced mask writer program in 2011 and 2012. In 2010, efforts will focus on identifying a funding model to address the investment to develop such a technology.

Step and Flash imprint lithography (SFIL) has reached a critical point in its development life cycle. Resolution and image fidelity have been well established, and progress is being made on both the process and template fronts. This simple technique has the potential to become the next generation lithography (NGL) choice for semiconductor manufacturing. Yet, despite the positive outlook, SFIL has very little industry support. Concerns about defectivity, throughput, overlay, template cost, infrastructure, and a host of other critical issues are legitimate. More important, however, is the severe shortage of publicly available data on SFIL for semiconductor applications, giving the false impression that it is still in its infancy. This paper discusses the current status of SFIL and shows where industry collaboration is needed to solve the critical issues and demonstrate that it is a viable NGL technology.

SEMATECH has initiated a nanoimprint program and started imaging experiments with a Molecular Imprints Imprio300TM system at the SEMATECH facility in Albany, NY. An overview of the SEMATECH nanoimprint development program is presented as well as an assessment of nanoimprint technology strengths and weaknesses. SEMATECH plans to explore many of the critical aspects of the nanoimprint process to drive key improvements in overlay, imprint mask cleaning, and defectivity toward making nanoimprint technology a cost-effective lithography strategy for CMOS development and manufacturing applications. Results of nanoimprint overlay with a previous level exposed on a 1.35NA immersion lithography scanner show it has noticeably improved over previous results with champion data in the 18nm range. Imprint mask cleaning on an automated tool has shown no measurable degradation of critical dimension or line width roughness after ten cleaning cycles.

The cost of ownership (COO) of candidate technologies for 32 nm and 22 nm half-pitch lithography is calculated. To more accurately compare technologies with different numbers of process steps, a model that includes deposition, etching, metrology, and other costs is created. Results show lithography COO for leading edge layers will increase by roughly 50% from the 45 nm to the 32 nm half-pitch nodes. Double patterning and extreme ultraviolet lithography (EUVL) technologies have roughly the same COO under certain conditions. For 22 nm half-pitch nodes, EUVL has a significant cost advantage over other technologies under certain mask cost assumptions. Double patterning, however, may be competitive under worst case EUVL mask cost assumptions. Sensitivity studies of EUVL COO to throughput and uptime show EUVL may be cost-competitive at lower uptime and throughput conditions. In spite of these higher costs, total lithography costs for 32 nm and 22 nm half-pitches remain within reach of the Moore's Law trend. Finally, the COO of 450 mm lithography is calculated and shows the expected cost reduction is between 0% and 15%.

Anticipating the cost of ownership (COO) of different lithography approaches into the future is an act of faith. It requires that one believe that all of the lithographic problems with next generation lithography (NGL) approaches will be sufficiently resolved to support the production of manufacturing wafers. This paper assumes that all of the necessary technologies will be available in the future and that the cost of the components can be extrapolated from historic cost trends. Mask and wafer costs of a single critical lithography layer for the 65, 45, 32 and 22 nm half-pitch (HP) nodes will be compared for immersion, double process (DP), double expose (DE), extreme ultraviolet (EUV), and imprint technologies. The mask COO analysis assumes that the basic yield of an optical mask is constant from node to node and that the infrastructure that allows this performance will be in place when the technologies are needed. The primary differences in mask costs among lithography approaches are driven by the patterning write time and materials. The wafer COO is driven by the mask cost (for the low wafer-per-mask use case), the lithography tool cost, and the effective wafers per hour (wph) for the lithography approach being considered.

Nanoimprinting lithography (NIL) is being evaluated as a possible method for meeting lithography requirements for semiconductor imaging at 32nm half-pitch nodes and below. NIL is included in the International Technology Roadmap for Semiconductors (ITRS) as a potential choice for advanced lithography. In this technology, the template, or mold, is a critical component in achieving the requirements for feature size and defectivity. Since NIL is a contact imaging technique, one of the issues is the high probability of defects while imprinting. Since the template is in contact with a fluid during the imaging process, maintaining the required template cleanliness needed to met the ITRS requirements without damaging or changing critical dimensions is an important process. In this paper we discuss the results obtained from several different NIL template cleaning methods using SEMATECH's Mask Blank Development Center facilities. The effectiveness of different operating conditions as well as several different chemistries is compared.

Critical dimension (CD) metrology is an important process step within the wafer fab. Knowledge of the CD values at resist level provides a reliable mechanism for the prediction of device performance. Ultimately tolerances of device electrical performance drive the wafer linewidth specifications of the lithography group. Staying within this budget is influenced mainly by the scanner settings, resist process and photomask quality. At the 65nm node the ITRS roadmap calls for sub-3nm photomask CD uniformity to support a sub-3nm wafer level CD uniformity. Meeting these targets has proven to be a challenge. What can be inferred from these specifications is that photomask level CD performance is the direct contributor to wafer level CD performance. With respect to phase shift masks, criteria such as phase and transmission control are also tightened with each technology node. A comprehensive study is presented supporting the use of photomask aerial image emulation CD metrology to predict wafer level Across Chip Linewidth Variation (ACLV). Using the aerial image can provide more accurate wafer level prediction because it inherently includes all contributors to image formation such as the physical CD, phase, transmission, sidewall angle, and other material properties. Aerial images from different photomask types were captured to provide across chip CD values. Aerial image measurements were completed using an AIMSTMfab193i with its through-pellicle data acquisition capability including the Global CDU MapTM software option for AIMSTM tools. The through-pellicle data acquisition capability is an essential prerequisite for capturing final CD data (after final clean and pellicle mounting) before the photomask ships or for re-qualification at the wafer fab. Data was also collected on these photomasks using a conventional CD-SEM metrology system with the pellicles removed. A comparison was then made to wafer prints demonstrating the benefit of using aerial image CD metrology.

Today novel RET solutions are gaining more and more attention from the lithography community that is facing new challenges in attempting to meet the new requirement of the SIA roadmap. Immersion, high NA, polarization, and mask topography, are becoming common place terminology as lithographers continue to explore these areas. Here with, we compare a traditional 6% MoSi based EAPSM reticle and a high transmission solution made of a SiON/Cr film stack. Insights into the manufacturability of high transmission material are provided. Test patterns have been analyzed to determine the overall impact of imaging performance when used with immersion scanners and polarized light. Some wafer results provide reliability of simulations, which are used to make further investigation on polarization and immersion effects.

The requirements for critical dimension control on gate layer for high performance products are increasingly demanding. Phase shift techniques provide aerial image enhancement, which can translate into improved process window performance and greater critical dimension (CD) control if properly applied. Unfortunately, the application of hard shifter technology to production requires significant effort in layout and optical proximity correction (OPC) application. Chromeless Phase Lithography (CPL) has several advantages over complementary phase mask (c:PSM) such as use of a single mask, and lack of phase placement 'coloring' conflicts and phase imbalance issues. CPL does have implementation issues that must be resolved before it can be used in full-scale production. CPL mask designs can be approached by separating features into three zones based on several parameters, including size relative to the lithographic resolution of the stepper lens, wavelength, and illumination conditions defined. Features are placed into buckets for different treatment zones. Zone 1 features are constructed with 100% transmission phase shifted structures and Zone 3 features are chrome (binary) structures. Features that fall into Zone 2, which are too wide to be defined using the 100% transmission of pure CPL (i.e. have negative mask error factor, MEEF) are the most troublesome and can be approached in several ways. The authors have investigated the application of zebra structures of various sizes to product type layouts. Previous work to investigate CPL using test structures set the groundwork for the more difficult task of applying CPL rules to actual random logic design layouts, which include many zone transitions. Mask making limitations have been identified that play a role in the zebra sizing that can be applied to Zone 2 features. The elimination of Zone 2 regions was also investigated in an effort to simplify the application of CPL and improve manufacturability of reticle through data enhancements.

The lithography prognosticator of the early 1980"s declared the end of optics for sub-0.5μm imaging. However, significant improvements in optics, photoresist and mask technology continued through the mercury lamp lines (436, 405 & 365nm) and into laser bands of 248nm and to 193nm. As each wavelength matured, innovative optical solutions and further improvements in photoresist technology have demonstrated that extending imaging resolution is possible thus further reducing k1. Several authors have recently discussed manufacturing imaging solutions for sub-0.3k1 and the integration challenges. The requirements stated in the ITRS roadmap for current and future technology nodes are very aggressive. Therefore, it is likely that high NA in combination with enhancement techniques will continue further for aggressive imaging solutions. Lithography and more importantly "imaging solutions" are driven by economics. The technology might be extremely innovative and "fun", however, if it's too expensive it may never see the light of scanner. The authors have investigated and compared the capability of high transmission mask technology and image process integration for the 45nm node. However, the results will be graded in terms of design, mask manufacturability, imaging performance and overall integration within a given process flow.© (2005) COPYRIGHT SPIE--The International Society for Optical Engineering. Downloading of the abstract is permitted for personal use only.

Today the industry is filled with intensity-balanced c:PSM and much more focus is being placed on innovative approaches such as CPL (and in conjunction with IML for Contacts) and tunable transmission embedded attenuating phase shift mask (TT-EAPSM). Each approach has its own merits and demerits depending on the manufacturing strategy and lithography performance required. Currently the only commercially available photomask blanks are different chrome thickness binary and 6% attenuating blanks using molybdenum-silicide, making the accessibility to alternate transmissions much more challenging. This paper investigates the mask manufacturability of a tunable transmission embedded attenuating phase shift mask. New film materials that are used in the mask blank manufacture are modeled, deposited and characterized to determine its ability to meet performance requirements. Sputtering models, by rate and gas component, determines film stacks with tunable transmissions and thicknesses. Chemical durability, etch selectivity and thickness are a few parameters of the films that have been characterized to enhance the manufacturability and process reliability of the masks. Lithography simulation models using measured optical properties were developed and test masks that include actual device designs were fabricated. Analysis of CD variation, pattern fidelity and process margin was performed using 3D mask simulation to understand the impact on 65nm design rules. Feasibility and performance of tunable transmission photomasks for use in design and lithography are verified. Moreover, the mask manufacturability and lithography performance is compared to other enhancement techniques and their merits presented.

This paper shows the capability of chromeless phase lithography (CPL) and is particularly focused on different strategies for optical proximity corrections (OPC). A chromeless phase database is easily obtained from the original layout by changing the chromium pattern into a phase pattern. However, a specific optical proximity correction has to be applied due to the phase effect and the high transmission of the mask. Mask Error Enhancement Factor (MEEF) and process window for CPL technology have been estimated through wafer exposures. Moreover, various optical proximity correction strategies have been explored through a comparison between phase and chromium features such as hammerhead, zebra and scattering bars 1,2. Indeed, depending on the density of the pattern, we can improve the contrast and the process window by changing the local transmission. The transmission can be controlled by the addition of sub resolution chromium feature such as zebra chromium transverse features on the line for dense pattern, or chromium scattering bars in the space for a sparse pattern, or chromium patches on the line end. From 65 nm node measurements and 45 nm node simulations, the authors will then present the most effective sub resolution pattern to implement.© (2005) COPYRIGHT SPIE--The International Society for Optical Engineering. Downloading of the abstract is permitted for personal use only.

Various types of line ends have been evaluated for either straight CPL mask or hybrid type builds. The authors will focus on image line end shortening and the impact of through dose and focus performance for very high NA ArF imaging. Simulations on test structures have been calculated along with in photoresist simulations to predict the impact on process window capability. Test structures have been designed and fabricated into a functional test for evaluation. Process evaluations have been completed and exposure-defocus window calculated.

Contact patterning for the 65nm device generation will be an exceedingly difficult task. The 2001 SIA roadmap lists the targeted contact size as 90nm with +/-10% CD control requirements of +/- 9nm 1 . Defectivity levels must also be below one failure per billion contacts for acceptable device yield. Difficulties in contact patterning are driven by the low depth of focus of isolated contacts and/or the high mask error factor (MEF) for dense contact arrays (in combination with expected reticle CD errors). Traditional contact lithography methods are not able to mitigate both these difficulties simultaneously. Inlaid metal trench patterning for the 65nm generation has similar lithographic difficulties though not to the extreme degree as contacts. We have investigated the use of CPL mask technology for ArF contact hole imaging for sub-100nm contact imaging. The author's activities have been focused on the design, fabrication and integration of imaging technology. In this paper the author's emphasis will be on issues related to pattern layout, mask fabrication and image processing.

Each generation of semiconductor device technology drive new and interesting resolution enhancement technology (RET's). The race to smaller and smaller geometry's has forced device manufacturers to k1's approaching 0.40. The authors have been investigating the use of Chromeless phase-shifting masks (CLM) exposed with ArF, high numerical aperture (NA), and off-axis illumination (OAI) has been shown to produce production worthy sub-100nm resist patterns with acceptable overlapped process window across feature pitch. There have been a number of authors who have investigated CLM in the past but the technology has never received mainstream attention due to constraints such as wet quartz etch during mask fabrication, limited approach to optical proximity correction (OPC), and exposure tool limitations such as on-axis illumination and too low of NA. With novel binary halftone OPC and a capable modern mask making process, it has become possible to achieve global and local pattern optimization of the phase shifter for a given layout especially for patterning features with dimension at sub-half-exposure wavelength. The authors have built a number of test structures that require superior 2D control for SRAM gate structures. In this paper the authors will focus on image process integration for the 65nm node. Emphasis on pattern layout, mask fabrication and image processing will be discussed. Furthermore, the authors will discuss defect printing, inspection and repair, mask error enhancement factor (MEEF) of 2D structures coupled with phase error, layout, and mask fabrication specifications.

Each generation of semiconductor device technology drive new and interesting resolution enhancement technology (RET’s). The race to smaller and smaller geometry’s has forced device manufacturers to k1’s approaching 0.40. The authors have been investigating the use of Chromeless phase-shifting masks (CPL) exposed with ArF, high numerical aperture (NA), and off-axis illumination (OAI) has been shown to produce production worthy sub-100nm resist patterns with acceptable overlapped process window across feature pitch. These new reticle technologies have many issues that are similar to simple binary masks. The authors have investigated the printability of defects in CPL mask technology. Programmed defects of various sizes and types have been simulated and printed for sub 100nm imaging. High resolution scanning electron microscopy has been used to characterize these defects and develop an understanding of size and type that prints. In this paper the authors will focus on image line end shortening and the impact of through dose and focus performance for very high NA ArF imaging. The authors have built a number of test structures that require superior 2D control for SRAM gate structures. Various types of line ends have been evaluated for either straight CPL mask or hybrid type builds.

As IC fabrication processes are maturing for the 130nm node, IC devices manufacturers are focusing on 90nm device manufacturing at ever-lower k 1 values. Driven by cost savings, many integrated device manufacturers (IDMs) and foundries are working toward patterning critical mask layers of 90nm designs using high numerical aperture KrF exposure tools. The goal of this study is to find out whether KrF can be successfully used instead of ArF for fabricating 90nm devices. This exercise will help to gain learning for the upcoming 65nm node, where the early manufacturing phase will also be carried out at a similar k 1 of near 0.3 using ArF. For high volume wafer production, the cost and throughput are in favor of using a single exposure PSM technique vs. the two masks and double exposure technique required for alternating phase shift masks (altPSM). The high mask cost of altPSM also discourages its use for low volume manufacturing. The two leading candidates candidates for 90nm node using KrF are: 6% attenuated PSM and CPL Technology. In this work, we present a methodology on how to use transmission tuning to achieve the best process latitude for patterning poly gate layer. First, we analyze the diffraction patterns from 6% attPSM and CPL mask features and identify the optimum transmission for various pitches. Next we describe how CPL mask can be used as a variable transmission attenuated mask to produce the best through pitch imaging performance and show a practical implementation method for applying to real device designs. Then we demonstrate how to integrate the optimized transmission tuning into the data process and OPC flow for generating CPL mask. Finally, we provide an example experimental result on a real device pattern.

Each generation of semiconductor device technology drive new and interesting resolution enhancement technology (RET’s). The race to smaller and smaller geometry’s has forced device manufacturers to k1’s approaching 0.40. The authors have been investigating the use of Chromeless phase-shifting masks (CLM) exposed with ArF, high numerical aperture (NA), and off-axis illumination (OAI) has been shown to produce production worthy sub-100nm resist patterns with acceptable overlapped process window across feature pitch. There have been a number of authors who have investigated CLM in the past but the technology has never received mainstream attention due to constraints such as wet quartz etch during mask fabrication, limited approach to optical proximity correction (OPC), and exposure tool limitations such as on-axis illumination and too low of NA. With novel binary halftone OPC and a capable modern mask making process, it has become possible to achieve global and local pattern optimization of the phase shifter for a given layout especially for patterning features with dimension at sub-half-exposure wavelength. The authors have built a number of test structures that require superior 2D control for SRAM gate structures. In this paper the authors will focus on image process integration for the 65nm node. Emphasis on pattern layout, mask fabrication and image processing will be discussed. Furthermore, the authors will discuss defect printing, inspection and repair, mask error enhancement factor (MEEF) of 2D structures coupled with phase error, layout, and mask fabrication specifications.

Each generation of semiconductor device technology drive new and interesting resolution enhancement technology (RET’s). The race to smaller and smaller geometries has forced device manufacturers to k1’s approaching 0.40. In this paper the authors will focus on the impact of mask exposure error factor (MEEF) through pitch for 120nm contacts with and without assist features. Experimental results show that although the addition of scatter bars improves depth of focus it has a negative effect on MEEF.

The minimum gate pitch for the 65nm device node will push 193nm lithography toward k1 ~ 0.35 with NA = 0.85. Previous work has analyzed the challenges expected for this generation. However, in the simplest terms, optical lithography for the 65nm node will be difficult. Lithographers are, therefore, looking into high-transmission attenuated phase shift mask (high-T attPSM), where T > 14%, to improve process margins. The benefits of a high-t attPSM are substantial, but drawbacks like inspection difficulty, defect free blanks manufacture, and sidelobe printing may make the use of such masks impractical. One possible solution to this problem is to employ medium transmission (med-T) attPSM, such as T = 9%, to image critical levels of the 65nm node with 193nm lithography. Earlier work shows that the problems High-T attPSMs face are manageable for med-T attPSM. Sidelobe printing in particular will be treated in this work with simulation and experiment. A primary goal of this effort is to determine if the lithographic benefit of moving from industry-standard 6% attPSM to 9% attPSM is worth the risks associated with such a transition. This goal will be met through a direct comparison of experimental 0.75NA 193nm λ results for 6% versus 9% attPSM on gate, contact/via, and metal layers at 65nm generation target dimensions with leading edge resists. Additional information on the inspectability and reticle blank manufacture of % AttPSM will also be given to provide a cohesive analysis of the transition tradeoffs.

Contact patterning for the 65nm device generation will be an exceedingly difficult task. The 2001 SIA roadmap lists the targeted contact size as 90nm with +/-10% CD control requirements of +/-9nm. Defectivity levels must also be below one failure per billion contacts for acceptable device yield. Difficulties in contact patterning are driven by the low depth of focus of isolated contacts and/or the high mask error (MEF) for dense contact arrays (in combination with expected reticle CD errors). Traditional contact lithography methods are not able to mitigate both these difficulties simultaneously. Inlaid metal trench patterning for the 65nm generation has similar lithographic difficulties though not to the extreme degree as seen with contacts. This study included the use of multiple, high transmission, 193nm attenuated phase shifting mask varieties to meet the difficult challenges of 65nm contact and trench lithography. Numerous illumination schemes, mask biasing, optical proximity correction (OPC), mask manufacturing techniques, and mask blank substrate materials were investigated. The analysis criteria included depth of focus, exposure latitude and MEF through pitch, reticle inspection, reticle manufacturability, and cost of ownership. The investigation determined that certain high transmission reticle schemes are strong contenders for 65nm generation contact and trench patterning. However, a number of strong interactions between illumination, OPC, and reticle manufacturing issues need to be considered.

The 65nm device generation will require steady improvements in lithography scanners, resists, reticles and OPC technology. 193nm high NA scanners and illumination can provide the desired dense feature resolution, but achieving the stringent overall 65nm logic product requirements necessitates a more coherent strategy of reticle, process, OPC, and design methods than was required for previous generations. This required integrated patterning solution strategy will have a fundamental impact on the relationship between design and process functions at the 65nm device node.

Each generation of semiconductor device technology drive new and interesting resolution enhancement technology (RET’s). The race to smaller and smaller geometry’s has forced device manufacturers to k1’s approaching 0.40. The authors have been investigating the use of Chromeless phase-shifting masks (CLM) exposed with ArF, high numerical aperture (NA), and off-axis illumination (OAI) has been shown to produce production worthy sub-100nm resist patterns with acceptable overlapped process window across feature pitch. There have been a number of authors who have investigated CLM in the past but the technology has never received mainstream attention due to constraints such as wet quartz etch during mask fabrication, limited approach to optical proximity correction (OPC), and exposure tool limitations such as on-axis illumination and too low of NA. With novel binary halftone OPC and a capable modern mask making process, it has become possible to achieve global and local pattern optimization of the phase shifter for a given layout especially for patterning features with dimension at sub-half-exposure wavelength. The authors have built a number of test structures that require superior 2D control for SRAM gate structures. In this paper the authors will focus on image process integration for the 65nm node. Emphasis on pattern layout, mask fabrication and image processing will be discussed. Furthermore, the authors will discuss defect printing, inspection and repair, mask error enhancement factor (MEEF) of 2D structures coupled with phase error, layout, and mask fabrication specifications.

The requirements stated in the ITRS roadmap for back-end-of-line imaging of current and future technology nodes are very aggressive. Therefore, it is likely that high NA in combination with enhancement techniques will be necessary for the imaging of contacts and trenches, pushing optical lithography into the low-k1 regime. In this paper, we focus more specifically on imaging solutions for contact holes beyond the 90 nm node using high NA ArF lithography, as this is currently seen as one of the major challenges in optical lithography. We investigate the performance of various existing enhancement techniques in order to provide contact holes imaging solutions in a k1 range from 0.35 to 0.45, using the ASML PAS5500/1100 0.75NA ArF scanner installed at IMEC. For various resolution enhancement techniques (RET), the proof of concept has been demonstrated in literature. In this paper, we propose an experimental one-to-one comparison of these RET’s with fixed CD target, exposure tool, lithographic process, and metrology. A single exposure through pitch (dense through isolated) printing solution is preferred and is the largest challenge. The common approach using a 6% attenuated phase-shifted mask (attPSM) with a conventional illumination fails. The advantages and drawbacks of other techniques are discussed. High transmission (17%) attenuated phase shift, potentially beneficial for part of the pitch range, requires conflicting trade-offs when looking for a single exposure through pitch solution. More promising results are obtained combining a BIM or a 6% attPSM with assist slots and off-axis illumination, yielding a depth of focus (DOF) at 8% exposure latitude (EL) greater than 0.31 μm from 200 nm pitch through isolated. Chromeless phase lithography (CPL) is also discussed with promising results obtained at the densest pitch. At a 0.4 k1, an experimental extrapolation to 0.85NA demonstrates that a pitch of 180 nm can be resolved with 0.4 μm DOF at 8% EL. For all of these imaging solutions, various metrics are studied to compare printing performance. In addition to process latitude, we consider forbidden pitches, sidelobes printability, and mask error enhancement factor (MEEF).

The challenges of low k1 lithography require unique solutions at all levels of the lithography process. Chromeless phase lithography (CPL) is a promising technique that uses a 2-beam imaging strategy and a unique OPC application for enhanced CD uniformity through pitch. It is particularly effective when combined with a high numerical aperture (NA) and off-axis illumination (OAI). In addition to its imaging benefits, CPL masks offer many advantages in the manufacturing of the mask over other approaches. The manufacturing strategy and methodology employed to fabricate CPL masks will be discussed. The technical challenges of mask production will also be highlighted. Application of CPL to production ArF images were characterized through simulations and experimental data demonstrating the capability of this technique to produce complex structures.

Semiconductor manufacturers are increasingly focusing on contact and via layers as the most difficult lithography pattern. Focus and exposure latitude, MEF, as well as iso-dense bias are challenges for contact patterning. This situation is only expected to worsen for the 65nm device generation where the 2001 SIA roadmap update lists the contact size as 90-100nm in 2004-2005. Thus, new contact pattern techniques with novel manufacturability are required. One possible avenue to meet these stringent process control requirements is the use of tri-tone high transmission attenuated phase shifting masks (tri-tone AttPSM) for the 65nm generation. Multilayered SiN/TiN (9%-18%) EAPSM materials to manufacture advanced reticles were used in this investigation. Extensive study during the photomask processing (Front End and Back End) to access any issues related to the making of High %T tri-tone product types was performed. Finally, the 2 prototype reticles were evaluated on a 193nm scanner (0.75NA) with various illumination settings to generate imaging to support the 65nm node technology generation.

The impact of flare on lithographic imaging has been the subject of increased investigation as critical dimension requirements and K1 factors continue to be reduced. All 'real world' lithographic systems include aberrations and non-uniformities that detract from the ability to produce the ultimate imaging possible. The increased acceptance of double exposure techniques, such as complementary phase shift, can greatly increase the sensitivities of the process by effectively doubling the flare exposure in each image. All optical imaging systems have some amount of stray light, or flare, that detracts from system performance, critical dimension (CD) control, and process latitude. The effects of flare are compounded with the use of multiple exposure processes are used since this doubles the amount of exposure energy going through the optics and therefore increase the amount of stray light. Flare was characterized on two 0.63NA 193nm lithographic scanners using two different measurement techniques. Using a double-exposure technique previously presented new data that characterizes the across slit flare performance of a 193nm lithography system is reported. Data showing the effect of lens contamination and cleaning is also presented. In addition, a different flare metrology technique based on MTF was used to characterize the flare effects at a range of spatial frequencies. Metrology requirements and limitations of each technique are also discussed.

We present a complete method for the characterization and modeling of flare based on the measurement of the modulation transfer function (MTF) of scanners. A point-spread function (PSF scat ) representing only the scattered light or flare in the tool is inferred by comparing the measured MTF with a calculated MTF for aberration-free imaging. This PSF scat is then used to predict the effect of flare for different layouts. In particular, local variations in pattern density are shown to couple with mid- and short-range flare and lead to significant CD non-uniformity across the field. Finally, we examine double exposure techniques that are sensitive to flare because of the total light reaching the wafer, from the two masking steps. Keywords: Lithography, Flare, Modulation Transfer Function, 1. INTRODUCTION As engineers develop KrF and ArF lithography processes with k 1 values around or below 0.4, the impact of flare on imaging needs to be addressed very carefully. In particular, the description of flare as a constant background is not a good approximation anymore. Tests that allow the measurement of scattered light at all scale lengths at the image plane will become essential for IC designers in order to predict the performance of OPC, phase-shift masks, or double exposure techniques. In the past, several authors have developed techniques to measure, characterize and model flare, using resist as a detector.

Alternating aperture phase shifting mask (AAPSM) technology is finding increased use in the patterning of critical layers due to the enhanced resolution and decreased linewidth variation characteristic of this technique. The potential advantages of AAPSM processes must be weighed against the increased complexity of reticle layout, higher reticle cost, and heightened sensitivity to parameters such as lens aberration. This work details the effect of shifter trench depth on patterning performance for the 100nm node. Data was collected at an exposure wavelength of 193nm using reticles built with deliberate errors in shifter trench depth. Differences in patterning performance observed as a result of these variations are compared with the impact predicted from modeling.

Examining features of varying pitch imaged using phase-shifting masks shows a pitch dependence on the transmission best suited for optimum imaging. The reason for this deals with the relative magnitude of the zero and higher diffraction orders that are formed as the exposing wavelength passes through the plurality of zero and 180-degree phase-shifted regions. Subsequently, some of the diffraction orders are collected and projected to form the image of the object. Chromeless Phase-Shift Lithography (CPL) deals with using halftoning structures to manipulate these relative magnitudes of these diffraction orders to ultimately construct the desired projected image. A key feature of CPL is that with the ability to manipulate the diffraction orders, a single weak phase-shifting mask can be made to emulate any weak phase-shifting mask and therefore the optimal imaging condition of any pattern can be placed on a single mask regardless of the type of weak phase-shifter that produces that result. In addition, these structures are used to render the plurality of size, shape and pitch such that the formed images produce their respective desired size and shape with sufficient image process tolerance. These images are typically made under identical exposure conditions, but not limited to single exposure condition. These halftoning structures can be used exterior, as assist features, or interior to the primary feature. These structures can range in transmission from 0% to 100% and they can be phase-shifted relative to the primary features or not. Thus CPL deals with the design, layout, and utilization of transparent and semi-transparent phase-shift masks and their use in an integrated imaging solution of exposure tool, mask and the photoresist recording media. This paper describes the method of diffraction matching, provides an example and reviews some experimental data using high numerical aperture KrF exposure.

Due to the challenging design rule and CD control requirements of the 100 nm device generation, a large number of complex patterning techniques are likely to be used for random logic devices. The complexity of these techniques places considerable strain upon model-based OPC software to identify and compensate for a wide range of printing non- idealities. Additionally, the rapidly increasing cost of advanced reticles has increased the urgency of obtaining reticles devoid of process limiting design or OPC errors. We have evaluated the capability of leading edge model-based OPC software to meet the challenging lithography needs of the 100 nm device generation. Specifically, we have implemented and verified model usefulness to correct for pattern deformation in complex binary gate, contact and via processes utilizing highly optimized illumination. Additionally, we present results showing the abilities of model-based methods to accurately find design related printing problems in complementary phase shift gate designs before they are committed to an expensive reticle.

Repair and printability of 193nm alternating aperture phase shift masks have been studied in detail in an effort to understand the overall production capability of these masks for wafer production at the 100nm node and below.

All optical imaging systems have some amount of stray light, or flare, that detracts from system performance, critical dimension (CD) control, and process latitude. The effects of flare increase when multiple exposure processes, such as complementary phase shift, are used since this doubles the amount of exposure energy going through the optics. Flare was characterized on several modern KrF and ArF exposure tools using a direct method of measurement. Flare is determined by measuring the reduction in the size of a 160 nm line as it is subjected to increasing dose from a second 'flare' exposure. The amount of flare is determined using regression between experimental and modeled data. Lithography modeling was used to quantify the amount of flare responsible for CD variation. This method allows evaluation of CD control degradation on actual features that are sized close to production feature size. The effects of substrate reflectance and mask loading were also studied. The results were compared to a published large pad flare measurement technique in common use.

Smaller device dimensions and tighter process control windows have created a need for CD metrology tools having higher levels of precision and accuracy. Furthermore, the need to detect and measure changes in feature profiles is becoming critical to in-line process control and stepper evaluation for sub-0.18μm technology. Spectroscopic CD (SCD ) is an optical metrology technique that can address these needs. This work describes the use of a spectroscopic CD metrology tool to measure and characterize a sub-0.18μm gate level focus and exposure matrix. The spectroscopic CD tool is used to characterize the focus and exposure windows for the process. The results include comparison to the established in-line CD-SEM, as well as a cross-section SEM. Repeatability and long-term stability data from a gate level nominal process are also presented.