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The paper develops a prediction model based on the surface electromyography (sEMG) signals to recognize the five different arm-related motions. We collect 100 groups of the three-channels signals on Biceps, Triceps, Brachioradialis as the raw data set. Then we extract four features from the data to describe the characteristics of different motions in the data set. In the pre-processing stage, we compare three types of EMD-based filtration methods to denoise signals and choose the most efficient one, then use principle component analysis to reduce the dimension of the data. We use three different methods to classify and predict the processed data for a higher accuracy. The contributions are following: This project successfully automated the pattern recognition of arm-related motions. Moreover, the project generated a valuable data set; Compared performances of EMD, EEMD and CEEMDAN in sEMG signals; Found that FCNN is the most accurate algorithm in this project. Future works include obtain more data from more volunteers to expand the data set.

This paper reports the design, fabrication, and test of a 3-D integrated uncooled focal plane array (FPA) using monocrystalline silicon diodes as thermosensitive devices. The diode array is fabricated from the silicon device layer of a silicon-on-insulator wafer, and the readout integrated circuits (ROICs) are fabricated on a bulk wafer using the CMOS technology. The silicon diode array is vertically integrated with the ROIC using the 3-D integration technology. Electroless nickel (Ni) plating is developed for fabricating substantial Ni posts to mechanically support the diode pixels to suspension and electrically connect the diode pixels to the ROIC. It allows the integration of monocrystalline device arrays with CMOS circuits fabricated using separate technologies and wafers in vertically suspended configuration. It also improves the filling factors of the FPA chips, shortens the wires between the diodes and the ROIC, and facilitates the releasing process to suspend the diode array. A $160 \times 120$ small-scale FPA has been developed as a test vehicle for concept verification. The test results and successful thermal imaging demonstrate the feasibility of the 3-D integration technology and verify the application of 3-D integration in the development of integrated FPAs using monocrystalline thermosensitive devices.

Silicon nanowire (SiNW) field-effect transistors (FETs) have been developed as various bio/chemical sensors due to their high sensitivity as a result of the huge surface-to-volume ratios. This paper presents a CMOS compatible sidewall mask technology (SMT) for top-down fabrication of SiNWs and a highly sensitive pH sensor based on SiNW FETs. The essence of SMT is to use stand-alone vertical sidewalls of a conformal thin film, fabricated by anisotropically etching away the planar part of the thin film deposited on a thin mesa, as hard masks for SiNW etching. As the feature size of the sidewalls, depending on the film thickness rather than lithography, can be controlled readily to tens to hundreds of nanometers by tailoring the film thickness, SMT allows high output and low cost fabrication of SiNWs without need of advanced lithography facilities. Complete SMT processes have been developed for fabrication of SiNW FETs, and pH sensors using SiNW FETs have been realized. Measurement results show that the pH sensors have good static characteristics and transient performance, and the sensitivity reaches 54.5 mV/pH for a wide range of pH values from 1 to 12, approaching the theoretical Nernstian limit.

Hand, foot, and mouth disease (HFMD) is a common infectious gastrointestinal disease in children under the age of 5. Many studies have documented that meteorological variables, especially temperature, are associated with HFMD. Since the general climate patterns occur as latitude increases, so latitude may indirectly influence the peak time of HFMD. The objective of this study was to explore the effect of latitude on the starting of an HFMD epidemic in Dalian, which can help in the development of an early warning model of HFMD in difference latitude districts. Spearman's rank correlation coefficient was used to analyze the tendency of HFMD incidence rate over the year. A circular distribution method was used to calculate the gold standard of beginning of the HFMD epidemic. A negative binomial regression model was used to establish the early warning of the starting of the HFMD epidemic. The annualized crude incidence rate of HFMD disease in Dalian, Liaoning Province, China as a whole was 169.14 per 100,000 from 2009 to 2013.The incidence rate of HFMD varied considerably by district during the study period, but there was no significant declining or rising trend in disease incidence over the years by district of Dalian. The circular statistical analysis results showed that there was latitudinal gradient in the starting of the HFMD epidemic except for region B; the starting time of HFMD epidemic of Region A was earlier than other regions range 9 days to 18 days. The starting time of the HFMD epidemic differs from region to region with different latitudes in Dalian, Liaoning Province, China. This result can provide a scientific basis for early warning of HFMD.

Organophosphate esters (OPEs) are widely used as flame retardants and plasticizers in consumer and industrial products. Human exposure to OPEs raises concerns due to their endocrine disruptive potentials. Till now, the effects of OPEs on thyroid hormones (THs) and the mediating role of oxidative stress in pregnant women have not been studied. In this study, prenatal urinary concentrations of OPE metabolites (mOPEs), levels of free triiodothyronine (FT3), free thyroxine (FT4), thyroid-stimulating hormone (TSH), and oxidative stress levels of 8-hydroxy-2-deoxy guanosine (8-OHdG) and malondialdehyde (MDA) were measured in pregnant women (n = 360) from a coastal urbanized region and moderate socioeconomic status. Neonatal TSH in heel blood was also measured in newborns (n = 309). Dibutyl phosphate (DBP) and diphenyl phosphate (DPHP) were extensively detected with a median creatinine-adjusted level of 0.19 μg/g and 0.66 μg/g, respectively, and the median of ∑mOPEs was 1.82 μg/g. DBP and DPHP were included in the analysis. The concentrations of DBP and DPHP were positively associated with either maternal or neonatal TSH levels, while not for maternal FT3 and FT4 levels. Positive associations for maternal and neonatal TSH were particularly observed in girls as stratified by newborn sex suggesting a sex-selective difference. Furthermore, 8-OHdG, the biomarker of DNA damage, was found to be a major mediator (>60%) for the association between neonatal TSH and DPHP, suggesting that DNA damage is involved in fetal thyroid function disruption. On the other hand, MDA showed a partially suppressing effect (

We have proposed a novel gate-controlled lateral thyristor (GC-LT) and a pixel circuit featuring intrinsic high dynamic range by multi-mode operation. The novel gate-controlled lateral thyristor structure with high sensitivity for weak light is designed. A cooperative pixel circuit is proposed to establish multi-sampling modes. Experimental results show that the gate-controlled lateral thyristor has high sensitivity for weak-light since the minimum distinguishable signal is as low as 1×10-9W/cm2 due to the cycle amplification between cross-coupled bipolar transistors inside the detector. In addition, more than four orders of light intensity from 10-6 to 10-2W/cm2 can be detected by linear mode and logarithmic mode. A high dynamic range more than 140dB are achieved using the pixel circuit by multi-mode operation.

A simple and efficient method for the base-mediated synthesis of unsymmetrical 1,3,5-triazin-2-amines has been developed. The protocol uses readily available imidates, guanidines, and amides or aldehydes as the starting materials, cesium carbonate as the base, no catalyst or additive is required, and the three-component reaction provides diverse 1,3,5-triazin-2-amines in moderate to good yields with tolerance of wide functional groups.

A series of novel N-methyl morpholine (Nmm) based ionic liquids with 1,2-propanediol group were synthesized and used as catalysts for Knoevenagel condensation at room temperature in water. Under the effect of the catalyst, various aldehydes or aliphatic ketones could react with a wide range of activated methylene compounds well, including malononitrile, alkyl cyanoacetate, cyanoacetamide, β-diketone, barbituric acid, 2-arylacetonitrile and thiazolidinedione. Furthermore, most of the products could be separated just by filtrating and washing with water. Additionally, the catalyst is recyclable and applicable for the large-scale synthesis.

SSDs are getting widely used in data centers. It is a critical issue to design efficient software for exploiting the benefits of fast SSD hardware. In this paper, we propose OCStore, an object store based on open-channel SSDs for distributed object storage system. OCStore manages the objects directly on raw flash memory, mitigating redundant functions across the object store, the file system, and the FTL layers. It provides streamed transactional update, which not only ensures the multi-page atomicity leveraging the non-overwrite flash write features, but also provides isolation for independent I/O streams while enabling parallel accesses to different channels. OCStore also coordinates different channels to enable transaction-aware scheduling, so as to reduce transaction-level latency and provide low response time to distributed storage. We implement OCStore in Linux kernel on the real open-channel SSDs, and evaluate them as OSDs in Ceph. Evaluations show that OCStore outperforms state-of-the-art object stores by 1.5x to 3.0x, while providing much lower and stable latencies, and decreases up to 70% write traffic under heavy workloads.

In this paper, a two-step RESET switching behavior of Ag/Al2O3/HfO2/Pt bilayer resistive random access memory (RRAM) devices is investigated. The interface between the two oxide layers is responsible for the special two-step RESET switching. When the conducting filaments have ruptured in the lower layer, the interface can protect the Ag ions of the filaments from breaking in the upper layer due to the trapped charges or defects at the interface. Therefore, a stable middle resistance state (MRS) is realized and the device exhibits a terrace-like I–V curve during the RESET operations. A filament-based switching mechanism combined with the electron hopping theory is proposed to explain the physical nature of the two-step RESET behavior. Furthermore, a good multi-level resistive switching performance with excellent endurance and retention reliability is obtained.

The effects and mechanisms responsible for charge lateral migration in 3D SONOS devices are studied in detail. We evaluated the electron lateral migration at room temperature and at 150 °C in 3D SONOS devices. Through interpretation of measurements and simulations, we found that lateral migration shows similar emission rates of Poole–Frenkel effect and therefore it is linked to the same trap energy profile. This feature should be included in a model to properly simulate 3D SONOS retention transients. Further experiments and simulations show no influence of SiN thickness nor P/E cycles on lateral migration.

NAND Flash has been widely used as storage solutions for portable system due to improvement on data throughput, power consumption and mechanical reliability. However, NAND Flash presents inevitable decline in reliability due to scaling down and multi-level cell (MLC) technology. High data retention error rate in highly stressed blocks causes a trend of stronger ECC deployed in system, with higher hardware overhead and spare bits cost. In this paper, a word line program disturbance (WPD) based data retention error recovery strategy, which induces extra electron injection to compensate floating gate electron leakage during long retention time, is proposed to reduce the data retention error rate and improve the retention reliability of highly scaled MLC NAND Flash memories. The proposed strategy is applied on 2×-nm MLC NAND Flash and the device one-year retention error rate after 3 K, 4 K, 5 K and 6 K P/E cycled decreases by 75.7%, 79.3%, 82.3% and 83.3%, respectively.

A 1G-cell NOR flash memory chip has been designed and fabricated successfully with 65 nm technology. To compromise the array efficiency and chip speed, the paper establishes an array model including parasitics of the whole array, and optimizes the sector structure as 512 wordlines (WLs) and 4096 bitlines (BLs). Furthermore, by adding other models of long and thin metal lines, we have analyzed the speed of critical circuit nodes. As a result, the agreement of WL delay between simulation and measurement verifies the accuracy of the array model and lines models. The test results indicate that the chip achieves random access time of 100 ns and page read time of 25 ns under 3.3 V voltage supply.

Dual supply voltage was a mature method to reduce the dynamic power of specific and programmable circuits, and the unsettled low voltage level (V L ) was proved to have impact on its effect. In this paper, a circuit-level power model is developed to estimate the optimal V L fast for field-programmable gate array (FPGA). The model is mainly based on the path delay distribution of applications and the delay function of the integrated circuit technology. It can also count minor factors, such as path overlap, transition density, and capacitance. Experiment was conducted on a 90-nm FPGA model using MCNC benchmark. The results showed that the proposed method could generate near optimum V L for most benchmarks. The best power reduction ratio is only 5.6% less than the gate-level heuristic method, which is relatively precise, but our method is ~100-10000 times faster. It implies that the dual voltage design with variable VL is a possible and promising low power method for field-programmable devices.

Through-silicon vias (TSVs) using benzocyclobutene (BCB)-liners as the insulator have the potential for reducing the TSV capacitances and the thermal expansion stresses. This paper reports the assessments of BCB-liner TSVs with respect to thermal and electrical properties. The C-V and I-V characteristics are measured at room temperature and at an elevated temperature as high as 125°C to characterize the electrical properties of capacitance and leakage current at different temperatures. Some C-V and I-V features associated with BCB-liners are discussed and the mechanisms are analyzed. Thermal cycling between -65°C and 150°C is performed, and the C-V and I-V characteristics are measured before and after thermal cycling to evaluate the thermomechanical stability of the BCB-liners, and the results show that the C-V and I-V properties are improved after thermal cycling. These preliminary results on the electrical and thermal properties of BCB-liner TSVs show that they have good thermal stability.

A new procedure to assess the impact of lateral charge migration from the overall retention transient is developed. This experimental procedure is designed to be applied on any 3D NAND string, and does not require devices specifically designed; this allows to assess the impact of lateral migration in realistic conditions. The experimental procedure relies on comparing retention loss of a standard sample with a “control sample” not suffering from lateral migration, thanks to a pre-conditioning operation. The pre-conditioning procedure to obtain the control samples is discussed in detail and demonstrated through measurements and simulations.

This paper presents a 65-nm 1-Gb NOR-type floating-gate flash memory, in which the cell device and chip circuit are developed and optimized. In order to solve the speed problem of giga-level NOR flash in the deep sub-micron process, the models of long bit-line and word-line are first given, by which the capacitive and resistive loads could be estimated. Based on that, the read path and key modules are optimized to enhance the chip access property and reliability. With the measurement results, the flash memory cell presents good endurance and retention properties, and the macro is operated with 1-µs/byte program speed and less than 50-ns read time under 3.3 V supply.

In this paper, we have studied the total ionizing dose (TID) radiation response up to 2 Mrad(Si) of silicon-oxide-nitride-oxide-silicon (SONOS) memory cells and memory circuits, fabricated in a 130 nm complimentary metal-oxide-semiconductor (CMOS) SONOS technology. We explored the threshold voltage (VT) degradation mechanism and found that the VT shifts of SONOS cells depend on the charge state; simply programming the cell to a higher VT cannot compensate for the radiation induced VT loss. The off-state current (Ioff) increase in the SONOS cell is also studied in this paper. Both VT and Ioff degradation would affect the memory system. Read data failures are mainly caused by VT shifts under irradiation, and program and erase failures are mainly caused by increased Ioff, which overloads the charge pumping circuit. By varying the reference current, our 4 Mb NOR flash chip has the potential to survive a radiation dose of 1 Mrad(Si) in read mode.

The total ionizing dose response against the γ ray of 3-D silicon-oxide-nitride-oxide-nitride (SONOS) cells with a vertical polysilicon channel was investigated. No leakage current increase or subthreshold slope degradation is observed up to the total ionizing dose of 1 Mrad(Si) even for devices scaled down to 22 nm, as the gate-all-around structure provides better control over the potential in the body, and shallow trench isolation oxide is not required. The threshold voltage (VT) shifts trend during radiation is similar to the behavior of 2-D cells, and can be well predicted with McWhorter's model. Benefiting from a larger initial memory window before irradiation, 3-D SONOS cells have a significant memory window of 4.5 V after exposure to a high radiation dose of 1 Mrad(Si). These results clearly indicate that 3-D SONOS devices are promising as radiation-tolerant memories.

A technical challenge in fabrication of ultra-thin sensor chip (UTSC) is to keep chip integrity in debonding the ultra-thin chips from grinding facilities. This paper presents a new debonding method by utilizing a thermally decomposable polypropylene carbonate (PPC), as the temporary bonding adhesive. Because PPC can readily decompose at relatively low temperature, this method can maintain the chip integrity even the chips have a thickness of tens of microns. UTSCs with thickness of 30μm have been achieved using this method, and stress sensors have been developed to verify the performance of UTSC. The experimental results show that the proposed method is able to fabricate UTSC with good flexibility and characterizations, demonstrating the newly proposed method an enabling technology for fabrication of sensors for flexible and wearable applications.

We present a monolithic integration of multiple sensors that have various structures and different packages. The multi sensors include an electrical field sensor (EFS) and accelerometers in a vacuum package and pressure, humidity, temperature sensors with direct contact with environment. To conduct the electrical signals from the vacuum package, three-dimensional (3-D) integration is implemented with a silicon interposer with through-silicon-vias (TSVs). The configuration of the multi sensor system, the co-design and co-fabrication, and packaging schemes are presented.

In this work, optimized signal transmission schemes are proposed to improve the signal transmission speed and area efficiency of high density embedded DRAM (eDRAM). As in the schemes, overdrive scheme is adopted to enhance the drive capability of read word-line (RWL) inverters and reduce inverters area overhead, optimized signal transmission path scheme is proposed to reduce signal transmission loading, and a Vth loss compensation and signal path pre-charge technology are also adopted to improve the data access speed. The proposed schemes are implemented in 1Mb eDRAM on 65nm CMOS technology node. Calculation and simulation results present 20% area reduction on RWL pull-down inverters and 10% data access speed improvement.