Search

The sidewall roughness of through-silicon vias (TSVs) plays a critical role in the reliability and integrity of signal transmission, particularly at high frequencies. In this study, we introduce a novel approach utilizing generalized closed-form expressions to assess the parasitic RLGC parameters resulting from the sidewall roughness of TSVs under high-frequency conditions. By comparing the calculated results for different sidewall roughness with the outcomes from full-wave electromagnetic (EM) simulations, a high degree of consistency is maintained. Simultaneously, the parasitic parameters showcase systematic variations that correspond to changes in sidewall roughness. Our findings underscore that the adverse impact of TSVs’ parasitic effects becomes more pronounced with heightened sidewall roughness. Importantly, the comparative analysis shows that the correction factor for inductance surpasses that of resistance, underscoring the significance of parasitic inductance. This finding attributes the primary source of parasitic effects to the parasitic inductance resulting from sidewall roughness. In addition, this study meticulously scrutinizes the experimental results, drawing comparisons against both calculated and simulated outcomes, resulting in a good degree of concurrence. This synchronization suggests that the proposed closed-form expressions adeptly capture the nuances of sidewall roughness in TSVs and thus prove highly suitable for scrutinizing a gamut of parasitic effects stemming from sidewall irregularities.

The sidewall roughness of through-glass vias (TGVs) at high frequencies significantly impacts the integrity and reliability of signal transmissions via the inductance and resistance-correction factors resulting from the combined effect of the skin depth and sidewall roughness. Here, to further investigate the generation and mechanism of the correction factors, a hemispherical physical model of the sidewall roughness of actual TGVs is proposed, and the ${RL}$ model comprising the skin depth and sidewall roughness is derived; the measured results were compared with the causal hemispherical model and the multilevel causal Huray model, and it was verified that the proposed hemispherical model can calculate the ${RL}$ parasitic parameters of TGV with high accuracy. Concurrently, the proposed hemispherical model confirms that the correction factor for internal inductance is larger than that for resistance; it can explore the main source of sidewall-roughness-induced parasitic effects. Moreover, the model offers a solution for reducing the sidewall-roughness-induced parasitic effects.

In glass-based 3-D integrated circuits (ICs), nonuniform through-glass vias (TGVs) contribute to increased delay, higher losses, and performance degradation, particularly notable in dense multilayer stacked circuits operating at high frequencies. To explore high-speed, low-loss vertical interconnections, we develop nonuniform TGVs double-layer vertical interconnect models and analyze impedance, insertion loss, and delay across various taper and sidewall roughness configurations. This study confirms a positive correlation among sidewall roughness, taper, and both loss and signal delay. Detailed examination of Smith charts for double-layer vertically interconnected TGVs further illustrates worsening impedance matching with increasing sidewall roughness and taper. In addition, we extract parasitic RLGC parameters, revealing that increased taper exacerbates parasitic effects induced by sidewall roughness, providing evidence for observed losses and delays. Our findings underscore the superior performance of cylindrical TGVs, advocating smaller taper and lower sidewall roughness for enhanced microwave performance in multilayer vertically interconnected devices. Experimental validation supports our conclusions, with measured results aligning well with simulations up to 40 GHz. Moreover, increased multilayer misalignment is confirmed to correlate with higher signal transmission loss and delay, while the loss positively correlates with the radius of pads between interconnection layers.

The integrity and reliability of signal transmission in glass 3-D integrated circuits (ICs) can be improved by studying the effect of sidewall roughness of through-glass vias (TGVs) on microwave performance. Thus, in this study, the effect of different sidewall roughness of TGVs on the electrical characteristics, such as loss, delay, and impedance correction factors, are analyzed by extracting S-parameters from the CPW-TGVs-CPW model. An accurate RLGC electrical model of TGVs that considers sidewall roughness is proposed. The correction factor of inductance is verified and found to be greater than that of resistance through simulation, physical measurements, and microscopic characterization analysis. Meanwhile, the sidewall roughness was improved by controlling the laser-induced wet etching (LIWE) process of TGVs. It was greatly reduced from $1.257 \mu \text{m}$ to 25 nm. The proposed electrical model is accurately verified below 40 GHz by extracting the electrical parameters of TGVs with different sidewall roughness.