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The infiltrative nature of lesions is a significant feature of malignant breast lesion on ultrasound image. Characterizing the infiltrative nature of lesions with computationally inexpensive and highly efficacious features is crucial for the realization of a computer-aided diagnosis system. In this study, the infiltrative nature is regarded as an energy that produces irregularly and considerably local variances in a 1-D signal. The local variances can be characterized by a few high octave energies (i.e., the channel energies close to low-frequency bands) in a 1-D discrete periodic wavelet transform. For computational cost reduction, high octave decomposition is performed by a reversible round-off 1-D nonrecursive discrete periodic wavelet transform. A test dataset of breast sonograms with the lesion contour delineated by an experienced physician and two inexperienced persons is built for feature efficacy evaluation. High individual performance results imply that the proposed feature is well correlated with the diagnosis of the experienced physician. Experimental results also reveal that with a great performance improvement, the proposed feature is suitable for the combination with some morphometric parameters. Index Terms--Breast lesion classification, octave energy, reversible round-off 1-D nonrecursive discrete periodic wavelet transform (RRO-NRDPWT), roughness description.

In this paper, a combined kernel architecture for efficiently decoding the residual data in the H.264/AVC baseline decoder is proposed. The kernel architecture in the H.264/AVC decoder consists of context-based adaptive variable length code (CAVLC) decoder, inverse quantization (IQ), and inverse transforms (IT) units. Since the decoding speeds of these kernel units vary with data, traditional methods require data buffers between these units. The first proposed architecture efficiently combines CAVLC decoding and IQ procedures. The multiple 2-D transforms architecture is applied to all inverse transforms, including the 4 x 4 inverse integer transform, the 4 x 4 inverse Hadamard transform and the 2 x 2 inverse Hadamard transform, to attain fewer gate counts than those of existing transform designs. Simulation results show that the total number of gates is 14.1k and the maximum operating frequency is 130 MHz. For real-time requirements, in the worst case, the proposed architectures can achieve the operation speed of the H.264/AVC decoder up to 4VGA@30 frames/sec in 4:2:0 format. Index Terms--H264/AVC, residue decoder, VLSI.

In this paper, efficient recursive structures for computing arbitrary length M-dimensional (M-D) discrete cosine transform (DCT) and its inverse DCT (IDCT) are proposed. The M-D DCT and IDCT are first converted into condensed one-dimensional (1-D) DCT and discrete sine transform (DST) with a regular preprocessing procedure. The recursive filters for condensed 1-D DCT/DST are then derived by using Chebyshev polynomials to compute M-D DCT/IDCT without data transposition. The proposed structures require fewer recursive loops than traditional 1-D recursive structures, which are realized in M passes and (M-1) data transposition by the so-called row-column approach. With advantages of fewer recursive loops and no transposition memory, the proposed structures attain more accurate results and less power consumption than traditional row-column structures. The proposed recursive M-D DCT/IDCT structures are suitable for very large-scale integration implementation due to regular and modular features. Index Terms--Discrete cosine transform (DCT), fast algorithm, inverse DCT (IDCT), multidimensional signal processing, recursive structure.

This paper presents a discrete-cosine transform (DCT)-based adaptive thresholding algorithm to achieve an effective binarization of video image for binary motion estimation (BME). The BME through the full search mechanism requires extremely low hardware complexity. Experimental results show that the proposed adaptive BME attains performance close to the 8-bit resolution ME for low motion sequences with full search strategy. Compared to the well-known single-layer BME, the proposed adaptive algorithm shows better peak signal-to-noise ratio performance and more robustness to complex images. Moreover, the proposed algorithm has a lower computational complexity that is suitable for VLSI implementation with a smaller hardware overhead. Index Terms--discrete cosine transform (DCT)-based adaptive thresholding (DAT), binary motion estimation (BME), fast motion estimation, fast motion search, DCT.

In this paper, new recursive structures for computing radix-r two-dimensional (2-D) discrete cosine transform (DCT) and 2-D inverse DCT (IDCT) are proposed. The 2-D DCT/IDCT are first decomposed into cosine-cosine and sine--sine transforms. Based on indexes of transform bases, the regular pre-addition preprocess is established and the recursive structures for 2-D DCT/IDCT, which can be realized in a second-order infinite-impulse response (IIR) filter, are derived without involving any transposition procedure. For computation of 2-D DCT/IDCT, the recursive loops of the proposed structures are less than that of one-dimensional DCT/IDCT recursive structures, which require data transposition to achieve the so-railed row--column approach. With advantages of fewer recursive loops and no transposition, the proposed recursive structures achieve more accurate results and less power consumption than the existed methods. The regular and modular properties are suitable for very large-scale integration (VLSI) implementation. By using similar procedures, the recursive structures for 2-D DST and 2-D IDST are also proposed. Index Terms--Discrete cosine transform (DCT), fast algorithm, inverse DCT (IDCT), multidimensional signal processing, recursive structure.

A CMOS rail-to-rail comparator operating at low-voltage supply by using a conventional fabrication process is proposed. Based on the comparator, an analog rank-order extractor with [kappa] winner-take-all capability is presented. An experimental chip was fabricated using 0.5 [micro]m CMOS technology. Measured results at 1-V supply voltage show a comparator response time of 4 [micro]s for 10-mV precision and that the extractor within 4[micro]s successfully identifies a 100-mV differential voltage among inputs to find a rank order of the input set. Index Terms--Comparator, low-voltage circuit, rank-order extractor.

In this paper, an adaptive postprocessor figured with discrete cosine transform (DCT)-based block classification to effectively remove the so-called blocky effect from compressed video sequences is proposed. The proposed DCT-based detection algorithms for both intraframes and interframes require much lower computation complexity than the spatial-domain approaches. In order to preserve the edge information, the adaptive postprocessor is also designed with a DCT-based edge detection mechanism such that a one-dimensional median filter can be adaptively adjusted to match with the edge orientation. Simulation results show that the proposed DCT-based detection algorithms accurately classifies smooth, edge, or nonsmooth blocks to help the adaptive postprocessor to effectively remove the blocky effect and sharply preserve the edge information. Index Terms--Adaptive median filter, transform coding, video coding, video signal processing.

In this paper, we present efficient recursive architectures for realizing the modified discrete cosine transform (MDCT) and the inverse MDCT (IMDCT) acquired in many audio coding systems. After data rearrangement, the MDCT and IMDCT can be represented as the Chebyshev polynomials such that we can efficiently implement them in the recursive structures. For verification, we design an ASIC to realize the recursive IMDCT. The analyzed results show that the proposed recursive infinite-impulse response (IIR) structures possess advantages of high efficiency and high throughput rate. The high regularity and modularity of the proposed recursive IMDCT and MDCT algorithms are other merits for very large scale integration implementation. Index Terms--Infinite-impulse response (IIR), inverse modified discrete cosine transform (IMDCT), modified discrete cosine transform (MDCT), recursive architecture.

In this paper, we propose transform-domain algorithms to effectively classify the characteristics of blocks and estimate the strength of the blocky effect. The transform-domain algorithms require much lower computational complexity and much less memory than the spatial ones. Along with the estimated blocky strength, we also propose an adaptive finite impulse response (FIR) filter to effectively remove the blocky effect. Simulation results show that the proposed algorithms sharply preserve the edge information and greatly improve the decoded image quality. Index Terms - Adaptive filters, transform coding, video coding, video signal processing.

The cerebellar model articulation controller (CMAC) neural network has the advantages of fast convergence speed and low computation complexity. However, it suffers from a low storage space utilization rate on weight memory. In this paper, we propose a direct weight address mapping approach, which can reduce the required weight memory size with a utilization rate near 100%. Based on such an address mapping approach, we developed a pipeline architecture to efficiently perform the addressing operations. The proposed direct weight address mapping approach also speeds up the computation for the generation of weight addresses. Besides, a CMAC hardware prototype used for color calibration has been implemented to confirm the proposed approach and architecture. Index Terms - CMAC, color calibration, high-level synthesis, pipeline architecture.

In this paper, a tree-based approach is proposed to design the fuzzy logic controller. Based on the proposed methodology, the fuzzy logic controller has the following merits: 1) the fuzzy control rule can be extracted automatically from the input-output data of the system and the extraction process can be done in one-pass; 2) owing to the fuzzy tree inference structure, the search spaces of the fuzzy inference process are largely reduced; 3) the operation of the inference process can be simplified as a one-dimensional matrix operation because of the fuzzy tree approach; 4) the controller has regular and modular properties, so it is easy to be implemented by hardware. Furthermore, the proposed fuzzy tree approach has been applied to design the color reproduction system for verifying the proposed methodology. The color reproduction system is mainly used to obtain a color image through the printer that is identical to the original one. In addition to the software simulation, an FPGA is used to implement the prototype hardware system for real-time application. Experimental results show that the effect of color correction is quite good and that the prototype hardware system can operate correctly under the condition of 30 MHz clock rate.

The 16/9 widescreen TV is popular in the recent market; however, its aspect ratio is not compatible with the conventional 4/3 SDTV program. In this paper, we propose a nonuniform conversion to efficiently display 4/3 SDTV programs on a 16/9 high-definition television (HDTV) monitor. For real time HDTV receivers, a parallel video converter is also proposed using nonuniform interpolation. To trade off complexity and performance, we only use one field-memory and one line-buffer for motion adaptation to interpolate pixels, which can be finished by the parallel computation kernel in one clock cycle. In order to combine parallel computation, the memory-slice method is employed, which is efficiently controlled by a state machine for nonuniform interpolation. With parallel conversion, a high-speed video converter can be achieved for advanced HDTV receivers.

In this paper, we propose the pipelined VLSI architecture and modular design to realize the coefficient-by-coefficient two-dimensional inverse discrete cosine transform (2-D IDCT) suggested by [1]. Based on parallel processing, the architecture of this chip is designed with a five-stage pipeline to meet the speed requirement for real-time applications. The key building modules of this chip include a generator of cosine angle index, a pipelined multiplier, and a matrix accumulator core. Satisfying the IEEE standard of 2-D IDCT in computational accuracy, this realized IDCT chip, which can work at a clock rate of higher than 50 MHz, is implemented by the CMOS technology in a reasonable die size. With modular and regular structures, the IDCT VLSI chip can be operated in progressive transform. In a real video decoding system, the average pixel-rate of the proposed 2-D IDCT chip achieves over 150 MHz for decoding intraframes and up to 400 MHz for decoding interframes.

Different from the previous PLA folding algorithms which perform row and column foldings independently, we propose an algorithm to obtain bipartite row or column folding result on the same graph. The PLA personality matrix is modeled as a graph and the folding problem is modeled as a partitioning problem. Experimental results show that this algorithm can lead a good guide to select row or column folding for reducing the chip area of the PLA efficiently.

H.264, MPEG-4 Part 10, is the latest digital video coding standard that achieves very high data compression by using several new coding features. One of the new features is variable block sizes for interframe coding to increase compression efficiency. However, to achieve this, the H.264 encoder employs a complex mode decision technique based on rate-distortion optimization (RDO) that requires high computational complexity, which significantly increases the encoder complexity. In this paper, we propose a classified region algorithm(CRA) that analyzes the spatial and temporal homogeneity of the block by using cross differences to reduce the number of modes that are required for RDO calculation in inter mode decision. The proposed low computational complexity algorithm significantly reduces the number of inter modes without affecting the video quality. The experimental results show that the proposed method is able to reduce complexity by up to 67% on average with negligible degradation in both objective and subjective quality.

The stability for cellular neural networks (CNNs) with time-varying delay is introduced by linear-matrix inequality. A sufficient condition related to the global asymptotic stability for delay CNNs is proposed. It is shown that the condition relies on the dependence of the delay. This condition is less restrictive than that given in the literature. Index Terms--Cellular neural networks (CNNs), linear-matrix inequality (LMI), stability.

In this paper, we propose a novel fuzzy logic controller, called linguistic hedge fuzzy logic controller, to simplify the membership function constructions and the rule developments. The design methodology of linguistic hedge fuzzy logic controller is a hybrid model based on the concepts of the linguistic hedges and the genetic algorithms. The linguistic hedge operators are used to adjust the shape of the system membership functions dynamically, and can speed up the control result to fit the system demand. The genetic algorithms are adopted to search the optimal linguistic hedge combination in the linguistic hedge module. According to the proposed methodology, the linguistic hedge fuzzy logic controller has the following advantages: 1) it needs only the simple-shape membership functions rather than the carefully designed ones for characterizing the related variables; 2) it is sufficient to adopt a fewer number of rules for inference; 3) the rules are developed intuitionally without heavily depending on the endeavor of experts; 4) the linguistic hedge module associated with the genetic algorithm enables it to be adaptive; 5) it performs better than the conventional fuzzy logic controllers do; and 6) it can be realized with low design complexity and small hardware overhead. Furthermore, the proposed approach has been applied to design three well-known nonlinear systems. The simulation and experimental results demonstrate the effectiveness of this design. Index Terms--Adaptive fuzzy logic controller, genetic algorithm, linguistic hedge.

In this brief, a current-mode Euclidean distance calculator circuit is proposed to play the role of a classifier. This classifier circuit is designed based on a subtracter circuit, an absoluter circuit, a squarer/divider circuit, and a square-rooter/multiplier circuit. The modular design of this classifier allows it to be easily extended for classification application with more input dimensions by doing some proper signal-scaling work due to the dynamic range limited by the square-rooter/multiplier circuit. This classifier circuit has been fabricated with a 0.6-[micro]m single-polysilicon double-metal CMOS process. Both simulation results and measurements of the implemented chip are presented to confirm the function of this classifier. Index Terms--Classifier circuit, current-mode circuit, Euclidean distance.