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Process variations in the manufacturing of digital circuits can be leveraged to design Physical Unclonable Functions (PUFs) that are extensively employed in hardware-based security. Different PUFs based on Magnetic Random-Access-Memory (MRAM) devices have been studied and proposed in the literature. However, most of these studies have been simulation-based, which do not fully capture the physical reality. We present experimental results on a PUF implemented on dies fabricated with a type of the MRAM technology namely Thermally-Assisted-Switching MRAM (TAS-MRAM). To the best of our knowledge, this is the first experimental validation of a TAS-MRAM-based PUF. We demonstrate how voltage values used for writing in the TAS-MRAM cells can make stochastic behaviors required for PUF design. The analysis of the obtained results provides some preliminary findings on the practical application of TAS-MRAM-based PUFs in authentication protocols. Besides, the results show that for key-generation protocols, one of the standard error correction methods should be employed if the proposed PUF is used.

Lightweight cryptography has recently emerged as a strong requirement for any highly constrained connected device; encryption/decryption processes must strike the balance between speed, area, power efficiency, and security robustness. The aim of this paper is to study the potential gains of the lightweight cryptography algorithms compared to the classic ones in hardware implementation. Advanced Encryption Standard (AES) as the standard, PRESENT and the very recently published GIFT are considered along with several optimized hardware versions of each one. Low- and high-security levels with 80- and 128-bit key length respectively are compared. They are all implemented on a Xilinx Kintex-7 FPGA, exploiting different slice configurations to evaluate their performances. The results show the expected benefits in terms of throughput and area, which allows selecting the best lightweight crypto-ciphers depending on the target device or application. In addition, correlation power analysis is performed on each cipher to estimate their resistance against side-channel analysis.

The complexity of embedded devices increases as today's applications request always more services. However, the power consumption of systems-on-chip has significantly increased due to the high-density integration and the high leakage power of current CMOS transistors. To address these issues, emerging technologies are considered. Spin-transfer torque magnetic random access memory (STT-MRAM) is seen as a promising alternative solution to traditional memories, thanks to its negligible leakage current, high density, and non-volatility. In this paper, we present the design and evaluation of a 128-kB STT-RAM in a 28-nm FD-SOI technology with SRAM-like interface for ultra-low power microcontrollers. With 0.9-pJ/bit read in 5 ns and 3-pJ/bit write in 10 ns, this embedded non-volatile memory is suitable for the devices that run at frequencies under 100 MHz. Considering a low-power application with duty-cycled behavior, we evaluate the STT-MRAM as a replacement of embedded Flash and SRAM by comparing single- and multi-memory architecture scenarios.

Noises exist in digital circuits can be leveraged as the source of entropy to design true random numbers generators (TRNGs), which is an important primitive component in cryptography and hardware-based security applications. In this paper, we present practical experiments and results of a TRNG implemented on magnetic random-access memory (MRAM) dies, fabricated by the thermally-assisted-switching MRAM (TAS-MRAM) technology. We, first, explain how one can find out a heating voltage value using that writing operations in the TAS-MRAM dies have a stochastic behavior. Then, we propose an improvement based on a feedback loop from being generated random bits. It helps to adjust the founded heating voltage value for writing operation with the aim of reaching the maximum entropy. Finally, we report the results of some post-processing methods, which are usually required in TRNGs to successfully pass the statistical test of NIST SP-800. The results show that one can generate random numbers with a high quality of randomness using the proposed TRNGs besides simple post-processing methods.

Static random access memory (SRAM) is the most commonly employed semiconductor in the design of on-chip processor memory. However, it is unlikely that the SRAM technology will have a cell size that will continue to scale below 45 nm, due to the leakage current that is caused by the quantum tunneling effect. Magnetic random access memory (MRAM) is a candidate technology to replace SRAM, assuming appropriate dimensioning given an operating threshold voltage. The write current of spin transfer torque (STT)-MRAM is a known limitation; however, this has been recently mitigated by leveraging perpendicular magnetic tunneling junctions. In this article, we present a comprehensive comparison of spin transfer torque-MRAM (STT-MRAM) and SRAM cache set banks. The non-volatility of STT-MRAM allows the definition of new instant on/off policies and leakage current optimizations. Through our experiments, we demonstrate that STT-MRAM is a candidate for the memory hierarchy of embedded systems, due to the higher densities and reduced leakage of MRAM.We demonstrate that adopting STT-MRAM in L1 and L2 caches mitigates the impact of higher write latencies and increased current draw due to the use of MRAM. With the correct system-on-chip (SoC) design, we believe that STT-MRAM is a viable alternative to SRAM, which minimizes leakage current and the total power consumed by the SoC.

Multiprocessor Systems-on-Chips (MPSoCs) offer superior performance while maintaining flexibility and reusability thanks to software oriented personalization. While most MPSoCs are today heterogeneous for better meeting the targeted application requirements, homogeneous MPSoCs may become in a near future a viable alternative bringing other benefits such as run-time load balancing and task migration. The work presented in this paper relies on a homogeneous NoC-based MPSoC framework we developed for exploring scalable and adaptive on-line continuous mapping techniques. Each processor of this system is compact and runs a tiny preemptive operating system that monitors various metrics and is entitled to take remapping decisions through code migration techniques. This approach that endows the architecture with decisional capabilities permits refining application implementation at run-time according to various criteria. Experiments based on simple policies are presented on various applications that demonstrate the benefits of such an approach.

With forecasted hundreds of processing elements (PEs), future embedded systems will be able to handle multiple applications with very diverse running constraints. Systems will integrate distributed decision capabilities. In order to control the power and temperature, dynamic voltage frequency scalings (DVFSs) are applied at PE level. At system level, it implies to dynamically manage the different voltage/frequency couples of each tile to obtain a global optimization. This paper introduces a scalable multiobjective approach based on game theory, which adjusts at run-time the frequency of each PE. It aims at reducing the tile temperature while maintaining the synchronization between application tasks. Results show that the proposed run-time algorithm requires an average of 20 calculation cycles to find the solution for a 100-processor platform and reaches equivalent performances when comparing with an offline method. Temperature reductions of about 23% were achieved on a demonstrative test-case.