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The reconfiguration algorithms have been extensively investigated to ensure the reliability and stability for the processor arrays with faults. It is important to reduce the power consumption, capacitance and communication costs in the processors by reducing the interconnection length of the VLSI array. This paper discusses the reconfiguration problem of the high-performance VLSI processor array under the row and column rerouting constraints. A novel method, making use the idea of network flow, is proposed in this paper. Firstly, a network flow model of the VLSI processor array is constructed, such that the high-performance VLSI target array can be obtained by utilizing the minimal cost flow algorithm. Secondly, we propose a new strategy for bottleneck row selection in the logical array using the minimum cut technique, which can find a more suitable bottleneck row. Finally, we conducted reliable experiments to clearly reveal the efficiency of the new rerouting scheme and algorithm in reducing the number of long interconnects. The experimental results show that, for a host array with size of 256×256, the number of long interconnects in the subarray can be reduced by up to 79.22% and 55.88% without performance penalty for random faults with density of 1% and 25% respectively, when compared with state-of-the-art. In addition, the proposed scheme improves existing algorithm in terms of subarray size. On a 256×256 host array with 25% faulty density, the average improvement in subarray size is up to 3.77% compared with state-of-the-art.

Mesh-connected processor array is an extensively investigated architecture in parallel processing. Massive studies have addressed the problem of using reconfiguration algorithms to solve the fault tolerance of faulty mesh-connected processor arrays. However, the subarrays generated by the previous studies still contain large interconnection length, which will lead to the increase of capacitance, power dissipation and dynamic communication cost. First, a mathematical model is established for the array reconfiguration. Then, the proposed method treats the interconnections between each PEs as a function with different integer variables, which can be solved by using effective integer programming techniques. Finally, an effective solver is called to find the optimal solution. Simulation results show that the proposed method can reduce the interconnection length of the array in the row and column directions simultaneously, thereby generating a subarray with the shortest interconnection length. On a 32 × 32 host array with fault density of 30%, the total interconnection length of the subarray can be reduced by 8.36% compared with state-of-the-art, and the average interconnection length can be reduced by 39.30%, which is more closer to the lower bound.

Reducing the number of visits to failure-free nodes can effectively reduce the reconstruction time of logical columns and improve the reconstruction efficiency. In this paper, we describe a new method to speed up the reconfiguration for the VLSI arrays. An efficient algorithm was proposed based on shortest path first principle for accelerating reconfiguration of VLSI processor subarrays with high power efficiency to meet the requirement of the power consumption of embedded system. The proposed algorithm greatly reduces the number of visits to the fault-free PEs for constructing a local optimal logical column and effectively reduces the construction time. Experimental results show that the proposed algorithm is capable of reducing the consumption time by 32.15% and reducing the numbers of visited PEs by 49.61% for a 128 × 128 host array with 20% falut rate.

The crowd flows prediction plays an important role in urban planning management and urban public safety. Accuracy is a challenge for predicting the flow of crowds in a region. On the one hand, crowd flow is influenced by many factors such as holidays and weather. On the other hand, sample data about crowd flows are generally high-dimensional, which not only has a negative impact on the prediction accuracy but also increases computational complexity. In this paper, an efficiency-enhanced model is constructed for predicting citywide crowd flows based on multi-source data using deep learning techniques. Specifically, a data reconstruction mechanism is built with Bernoulli restricted Boltzmann machine (BRBM), for the purpose of reducing the dimension of sample data. A collaborative prediction mechanism is introduced to improve the prediction accuracy of crowd flows, in which a spatio-temporal data oriented prediction model is constructed based on bottleneck residual network that can reduce the effectively computational complexity of model training, and an auxiliary prediction to further optimize the prediction accuracy based on the fully-connected network. The proposed method is evaluated by using two open datasets. The experimental results show that our method can significantly improve the prediction accuracy and reduce the training time of the prediction model, compared with other methods.

Reconfiguring a high-performance subarray of a VLSI array with faults is to construct a maximum target array with the minimum number of long interconnects, which can reduce communication costs, capacitance and dynamic energy dissipation. An existing work proved that the high performance VLSI subarray can be constructed in polynomial time using network flow algorithm. However, because of the disadvantage of the previous network model and the low-performing of standard network flow algorithms for reconfiguration, the efficiency of these algorithms is poor for constructing the high performance VLSI subarray. In this paper, we present an efficient multiple shortest augmenting paths algorithm for rapidly constructing high performance VLSI array. Firstly, we proposed an efficient data structure to construct the network model of the VLSI array with faults, which can dramatically reduce the size of the model compared with previous algorithm. Secondly, a multiple shortest augmenting path algorithm based on the new data structure is proposed, which can significant reduce the running time. Finally, we conduct solid experiments to highlight the efficiency of the proposed method in terms of the running time compared to the standard network flow algorithms. The experimental results show that on a 64 × 64 host array with 0.1% faults, the size of the network model can be reduced by about 50% and the average improvements in running time is up to 85.10% compared with four standard network flow algorithms.

This paper designs a real-time video stream-oriented action recognition platform, namely SmartCamera. It aims to detect target actions in real-time in a resource-constrained edge environment. The SmartCamera adopts 3D convolutional network-based sliding window as the classification model of actions, and introduces a flexible sliding window localization method to reduce the computational complexity of action recognition without harming behavioral consistency. The prototype of SmartCamera mainly includes five modules: Real-time Video Stream Collection, Video Stream Preprocessing, Action Recognition, Sliding Window Localization, User Interface. The preliminary evaluation shows that the system can detect target actions with an acceptable accuracy and latency.

In this paper, we investigated the technique for improving the reliability of 3-D processor with faults by reconfiguring a 3-D fault-free subarray utilizing as many nonfaulty process elements (PEs) as possible. A novel flexible rerouting scheme is proposed, which makes the PEs can be rerouted or bypassed in three dimensions, hence increasing the number of neighbors of each element to construct a logical array. Under this scheme, an efficient heuristic algorithm is presented to construct a logical array. The experimental results show that the proposed algorithm under flexible rerouting scheme can produce logical arrays with higher harvest from the host arrays with faults for the random fault scenarios, the improvement is by up to 46.47% compared to the state-of-the-arts.

We demonstrate reconfigurable unidirectional propagation of electromagnetic waves in waveguide channels sandwiched by two dielectric photonic crystal (PC) slabs or magnetic PC (MPC) slabs, where the extrinsic and intrinsic responses emerge in two kinds of systems. Concretely, the unidirectionality of the MPC system originates from the time-reversal symmetry breaking nature of magnetic material, while in the dielectric PC system, the unidirectionality is achieved by active control of two separated line sources. The results indicate that in the MPC based system, not only the amplitude but also the directionality of the guiding electromagnetic waves is flexibly regulated by controlling the separation and phase difference of two active line sources. However, the directionality in the MPC based system is determined by the magnetization due to the intrinsic unidirectionality of the magnetic system, but for the dielectric PC based system, directionality is controlled by active sources. The introduction of a second line source in the MPC based system can result in two remarkably different consequences. On one hand, the directionality can be switched from forward to backward propagation by reversing magnetization. On the other hand, the same operation results in the transition from unidirectional propagation to localization of the electromagnetic waves by dynamically controlling two active sources. The functionality and flexibility in the present systems might find potential applications in microwave photonics and integrated photonics.