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301 results on '"Linares-Barranco, B"'

1. A CMOL-Like Memristor-CMOS Neuromorphic Chip-Core Demonstrating Stochastic Binary STDP

Author

Camuñas-Mesa, L. A., Vianello, E., Reita, C., Serrano-Gotarredona, T., and Linares-Barranco, B.

Subjects
Computer Science - Emerging Technologies, Electrical Engineering and Systems Science - Image and Video Processing, Electrical Engineering and Systems Science - Signal Processing, Electrical Engineering and Systems Science - Systems and Control
Abstract

The advent of nanoscale memristors raised hopes of being able to build CMOL (CMOS/nanowire/moLecular) type ultra-dense in-memory-computing circuit architectures. In CMOL, nanoscale memristors would be fabricated at the intersection of nanowires. The CMOL concept can be exploited in neuromorphic hardware by fabricating lower-density neurons on CMOS and placing massive analog synaptic connectivity with nanowire and nanoscale-memristor fabric post-fabricated on top. However, technical problems have hindered such developments for presently available reliable commercial monolithic CMOS-memristor technologies. On one hand, each memristor needs a MOS selector transistor in series to guarantee forming and programming operations in large arrays. This results in compound MOS-memristor synapses (called 1T1R) which are no longer synapses at the crossing of nanowires. On the other hand, memristors do not yet constitute highly reliable, stable analog memories for massive analog-weight synapses with gradual learning. Here we demonstrate a pseudo-CMOL monolithic chip core that circumvents the two technical problems mentioned above by (a) exploiting a CMOL-like geometrical chip layout technique to improve density despite the 1T1R limitation, and (b) exploiting a binary weight stochastic Spike-Timing-Dependent-Plasticity (STDP) learning rule that takes advantage of the more reliable binary memory capability of the memristors used. Experimental results are provided for a spiking neural network (SNN) CMOL-core with 64 input neurons, 64 output neurons, and 4096 1T1R synapses, fabricated in 130nm CMOS with 200nm-sized Ti/HfOx/TiN memristors on top. The CMOL-core uses query-driven event read-out, which allows for memristor variability insensitive computations., Comment: accepted for IEEE Journal on Emerging Topics in Circuits and Systems

Published
2022

2. Implementation of binary stochastic STDP learning using chalcogenide-based memristive devices

Author

Mohan, C., Camuñas-Mesa, L. A., de la Rosa, J. M., Serrano-Gotarredona, T., and Linares-Barranco, B.

Subjects
Computer Science - Emerging Technologies, Electrical Engineering and Systems Science - Systems and Control
Abstract

The emergence of nano-scale memristive devices encouraged many different research areas to exploit their use in multiple applications. One of the proposed applications was to implement synaptic connections in bio-inspired neuromorphic systems. Large-scale neuromorphic hardware platforms are being developed with increasing number of neurons and synapses, having a critical bottleneck in the online learning capabilities. Spike-timing-dependent plasticity (STDP) is a widely used learning mechanism inspired by biology which updates the synaptic weight as a function of the temporal correlation between pre- and post-synaptic spikes. In this work, we demonstrate experimentally that binary stochastic STDP learning can be obtained from a memristor when the appropriate pulses are applied at both sides of the device.

Published
2021
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3. A memristive nanoparticle/organic hybrid synapstor for neuro-inspired computing

Author

Alibart, F., Pleutin, S., Bichler, O., Gamrat, C., Serrano-Gotarredona, T., Linares-Barranco, B., and Vuillaume, D.

Subjects
Condensed Matter - Mesoscale and Nanoscale Physics, Condensed Matter - Disordered Systems and Neural Networks, Condensed Matter - Materials Science, Computer Science - Emerging Technologies, Quantitative Biology - Neurons and Cognition
Abstract

A large effort is devoted to the research of new computing paradigms associated to innovative nanotechnologies that should complement and/or propose alternative solutions to the classical Von Neumann/CMOS association. Among various propositions, Spiking Neural Network (SNN) seems a valid candidate. (i) In terms of functions, SNN using relative spike timing for information coding are deemed to be the most effective at taking inspiration from the brain to allow fast and efficient processing of information for complex tasks in recognition or classification. (ii) In terms of technology, SNN may be able to benefit the most from nanodevices, because SNN architectures are intrinsically tolerant to defective devices and performance variability. Here we demonstrate Spike-Timing-Dependent Plasticity (STDP), a basic and primordial learning function in the brain, with a new class of synapstor (synapse-transistor), called Nanoparticle Organic Memory Field Effect Transistor (NOMFET). We show that this learning function is obtained with a simple hybrid material made of the self-assembly of gold nanoparticles and organic semiconductor thin films. Beyond mimicking biological synapses, we also demonstrate how the shape of the applied spikes can tailor the STDP learning function. Moreover, the experiments and modeling show that this synapstor is a memristive device. Finally, these synapstors are successfully coupled with a CMOS platform emulating the pre- and post-synaptic neurons, and a behavioral macro-model is developed on usual device simulator., Comment: A single pdf file, with the full paper and the supplementary information; Adv. Func. Mater., on line Dec. 13 (2011)

Published
2011
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8. Inter-spike-intervals Analysis of Poisson Like Hardware Synthetic AER Generation

Author

Linares-Barranco, A., Oster, M., Cascado, D., Jiménez, G., Civit, A., Linares-Barranco, B., Hutchison, David, editor, Kanade, Takeo, editor, Kittler, Josef, editor, Kleinberg, Jon M., editor, Mattern, Friedemann, editor, Mitchell, John C., editor, Naor, Moni, editor, Nierstrasz, Oscar, editor, Pandu Rangan, C., editor, Steffen, Bernhard, editor, Sudan, Madhu, editor, Terzopoulos, Demetri, editor, Tygar, Dough, editor, Vardi, Moshe Y., editor, Weikum, Gerhard, editor, Cabestany, Joan, editor, Prieto, Alberto, editor, and Sandoval, Francisco, editor

Published
2005
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16. Neutron-Induced, Single-Event Effects on Neuromorphic Event-Based Vision Sensor: A First Step and Tools to Space Applications

Author

Roffe, S, Akolkar, H, George, AD, Linares-Barranco, B, Benosman, RB, Roffe, S, Akolkar, H, George, AD, Linares-Barranco, B, and Benosman, RB

Abstract

This paper studies the suitability of neuromorphic event-based vision cameras for spaceflight and the effects of neutron radiation on their performance. Neuromorphic event-based vision cameras are novel sensors that implement asynchronous, clockless data acquisition, providing information about the change in illuminance ≥ 120dB with sub-millisecond temporal precision. These sensors have huge potential for space applications as they provide an extremely sparse representation of visual dynamics while removing redundant information, thereby conforming to low-resource requirements. An event-based sensor was irradiated under wide-spectrum neutrons at Los Alamos Neutron Science Center and its effects were classified. Radiation-induced damage of the sensor under wide-spectrum neutrons was tested, as was the radiative effect on the signal-to-noise ratio of the output at different angles of incidence from the beam source. We found that the sensor had very fast recovery during radiation, showing high correlation of noise event bursts with respect to source macro-pulses. No statistically significant differences were observed between the number of events induced at different angles of incidence but significant differences were found in the spatial structure of noise events at different angles. The results show that event-based cameras are capable of functioning in a space-like, radiative environment with a signal-to-noise ratio of 3.355. They also show that radiation-induced noise does not affect event-level computation. Finally, we introduce the Event-based Radiation-Induced Noise Simulation Environment (Event-RINSE), a simulation environment based on the noise-modelling we conducted and capable of injecting the effects of radiation-induced noise from the collected data to any stream of events in order to ensure that developed code can operate in a radiative environment. To the best of our knowledge, this is the first time such analysis of neutron-induced noise has been perfor

Published
2021

31. Fast and compact simulation models for a variety of FET nano devices by the CMOS EKV equations

Author

Serrano-Gotarredona, T., Linares-Barranco, B., Agnus, G., Vincent Derycke, Bourgoin, J. -P, Alibart, F., Vuillaume, D., Sohn, J., Bendall, J., Welland, M. E., Gamrat, C., Institut d’Électronique, de Microélectronique et de Nanotechnologie - UMR 8520 (IEMN), and Centrale Lille-Institut supérieur de l'électronique et du numérique (ISEN)-Université de Valenciennes et du Hainaut-Cambrésis (UVHC)-Université de Lille-Centre National de la Recherche Scientifique (CNRS)-Université Polytechnique Hauts-de-France (UPHF)

Subjects
Computer Science::Emerging Technologies, Hardware_INTEGRATEDCIRCUITS, Hardware_PERFORMANCEANDRELIABILITY, Hardware_LOGICDESIGN
Abstract

In this paper we explore the possibility of using the equations of a well known compact model for CMOS transistors as a parameterized compact model for a variety of FET based nano-technology devices. This can turn out to be a practical preliminary solution for system level architectural researchers, who could simulate behaviourally large scale systems, while more physically based models become available for each new device. We have used a four parameter version of the EKV model equations and verified that fitting errors are similar to those when using them for standard CMOS FET transistors. The model has been used for fitting measured data from three types of FET nano-technology devices obeying different physics, for different fabrication steps, and under different programming conditions. © 2009 IEEE NANO Organizers.

Published
2009

32. CAVIAR: a 45k neuron, 5M synapse, 12G connects/s AER hardware sensory-processing-learning-actuating system for high-speed visual object recognition and tracking

Author

Serrano-Gotarredona, R, Oster, M, Lichtsteiner, P, Linares-Barranco, A, Paz-Vicente, R, Gomez-Rodriguez, F, Camuñas-Mesa, L, Berner, R, Rivas, M, Delbruck, T, Liu, S C, Douglas, R J, Hafliger, P, Moreno, G, Civit, A, Serrano-Gotarredona, T, Acosta-Jimenez, A, Linares-Barranco, B, University of Zurich, and Serrano-Gotarredona, R

Subjects
1712 Software, 1705 Computer Networks and Communications, 1706 Computer Science Applications, neuromorphic AER system, 570 Life sciences, biology, 1702 Artificial Intelligence, 10194 Institute of Neuroinformatics
Published
2009

33. Inter-spike-intervals analysis of AER Poisson like generator hardware

Author

Linares-Barranco, A, Oster, M, Cascado, D, Jimenez, G, Civit, A, Linares-Barranco, B, University of Zurich, and Linares-Barranco, A

Subjects
2805 Cognitive Neuroscience, 1706 Computer Science Applications, 570 Life sciences, biology, 1702 Artificial Intelligence, 10194 Institute of Neuroinformatics
Published
2007

39. Neuromorphic Silicon Neuron Circuits

Author

Boahen, K, Wang, Y, Wijekoon, J, Serrano-Gotarredona, T, Saighi, S, Folowosele, F, Hynna, K, Arthur, J, Cauwenberghs, G, Schemmel, J, Renaud, S, Häfliger, P, Dudek, P, Liu, S-C, Delbruck, T, Etienne-Cummings, R, van Schaik, A, Hamilton, T J, Linares-Barranco, B, Indiveri, G, Boahen, K, Wang, Y, Wijekoon, J, Serrano-Gotarredona, T, Saighi, S, Folowosele, F, Hynna, K, Arthur, J, Cauwenberghs, G, Schemmel, J, Renaud, S, Häfliger, P, Dudek, P, Liu, S-C, Delbruck, T, Etienne-Cummings, R, van Schaik, A, Hamilton, T J, Linares-Barranco, B, and Indiveri, G

Abstract

Hardware implementations of spiking neurons can be extremely useful for a large variety of applications, ranging from high-speed modeling of large-scale neural systems to real-time behaving systems, to bidirectional brain–machine interfaces. The specific circuit solutions used to implement silicon neurons depend on the application requirements. In this paper we describe the most common building blocks and techniques used to implement these circuits, and present an overview of a wide range of neuromorphic silicon neurons, which implement different computational models, ranging from biophysically realistic and conductance-based Hodgkin–Huxley models to bi-dimensional generalized adaptive integrate and fire models. We compare the different design methodologies used for each silicon neuron design described, and demonstrate their features with experimental results, measured from a wide range of fabricated VLSI chips.

Published
2011

48. Confession session: Learning from others mistakes

Author

Abshire, P., primary, Bermak, A., additional, Berner, R., additional, Cauwenberghs, G., additional, Chen, S., additional, Christen, J. B., additional, Constandinou, T., additional, Culurciello, E., additional, Dandin, M., additional, Datta, T., additional, Delbruck, T., additional, Dudek, P., additional, Eftekhar, A., additional, Etienne-Cummings, R., additional, Indiveri, G., additional, Law, M.K., additional, Linares-Barranco, B., additional, Tapson, J., additional, Tang, W., additional, and Zhai, Y., additional

Published
2011
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49. MOSFET mismatch in weak/moderate inversion: model needs and implications for analog design

Author

UCL - FSA/ELEC - Département d'électricité, Vancaillie, L., Silveira, F., Linares-Barranco, B., Serrano-Gotarredona, T., Flandre, Denis, ESSCIRC 2004 - 29th European Solid-State Circuits Conference, UCL - FSA/ELEC - Département d'électricité, Vancaillie, L., Silveira, F., Linares-Barranco, B., Serrano-Gotarredona, T., Flandre, Denis, and ESSCIRC 2004 - 29th European Solid-State Circuits Conference

Abstract

Based on mismatch measurements performed on very different CMOS technologies and large operating temperature range, we propose to model more adequately the mismatch in weak and moderate inversion by adding a new term related to the mismatch of the body effect factor dependence on the gate voltage. The model is introduced in a top-down analog design methodology, applied to the current mirror case, revealing some nonobvious design rules as well as typical misconceptions., Anglais

Published
2003

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