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Los controles de capitales están nuevamente en la agenda de política e incluso las instituciones multilaterales de créditos reconocen su utilidad. Los controles no siempre se pueden implementar libremente. La estructura institucional asociada a los Acuerdos de Libre Comercio y los Acuerdos Bilaterales de Inversión pueden limitar severamente la posibilidad de regular la cuenta capital y al sistema financiero. Tras revisar la literatura sobre la liberalización de la cuenta capital, los controles de capitales, la administración del tipo de cambio y las políticas macro-prudenciales, este trabajo discute las limitaciones asociadas a estos acuerdos. Capital controls are once again on the policy agenda and even multilateral credit institutions recognize their usefulness. Controls can not always be freely implemented. The institutional structure associated with Free Trade Agreements and Bilateral Investment Agreements can severely limit the possibility of regulating the capital account and the financial system. After reviewing the literature on the liberalization of the capital account, capital controls, the administration of the exchange rate and macro-prudential policies, this paper discusses the limitations associated with these agreements. Fil: Stanely, Leonardo. Centro de Estudios de Estado y Sociedad; Argentina Fil: Libman, Emiliano. Centro de Estudios de Estado y Sociedad; Argentina. Universidad Nacional de San Martín; Argentina. Consejo Nacional de Investigaciones Científicas y Técnicas; Argentina

Existing empirical studies have focused on determinants of investment. We focus instead on episodes of accelerated capital stock growth that last eight years or longer. We find that episodes are relatively common, even in low growth regions, but more so in middle income and Asian countries. After identifying 175 such episodes between 1950-2014, we employ probit analysis to explore their characteristics. Turning points in investment tend to be preceded by undervalued real exchange rates, macroeconomic stability (low inflation), and net capital outflows (especially portfolio outflows). We also find strong evidence for a negative correlation with the capital to output ratio and per capita GDP, and a positive correlation with a human capital index. Investment surges appear to be associated with accelerated structural change in the economy.

Technology advancements allowed more transistors to be packed in a smaller area, while the improved performance helped in achieving higher clock frequencies. This, unfortunately led to a power density problem, forcing processor industry to lower the clock frequency and integrate multiple cores on the same die. Depending on core characteristics, the multiple cores in the die could be symmetric or asymmetric. Asymmetric multi-core processors (AMPs) have been proposed as an alternative to symmetric multi-cores to improve power efficiency. AMPs comprise of cores that implement the same ISA, but differ in performance and power characteristics due to varying sizes of micro-architectural resources. As the computational bottleneck of a workload shifts from one resource to another during its course of execution, reassigning it to another core (where it runs more efficiently), can improve the overall power efficiency. Thus achieving high power efficiency in AMPs requires (i) a diverse set of cores that are optimized for various program phases, (ii) runtime analysis to determine the best core to run on, and (iii) low overhead of re-assigning a thread to a different core type. Decisions to swap threads between AMPs are made at coarse grain granularity of millions of instructions, to mitigate the impact of thread migration overhead. But the computational needs of the program rapidly change during the course of its execution. The best core configuration for an application such that, both power consumption and performance are optimized, changes over time rapidly at fine granularity of thousands of instructions. This dissertation explores ways to design core micro-architecture such that high power efficiency could be achieved, if switching overhead could be lowered, enabling fine grain switching. To take advantage of power saving opportunities at fine grain granularity, this thesis explores reconfigurable/morphable architectures where core resources are reconfigured on demand to suit the needs of the executing application. At first, we explore reconfigurable architectures consisting of two kinds of cores: out-of-order (OOO) big cores and in-order (InO) small cores. The big cores provide higher performance while the small cores are more power efficient. In this proposed architecture, OOO core reconfigures into InO core at run time. Our proposed online management scheme decides to switch between these core types such that we obtain significant power benefits without impacting performance. We also observe that, resource requirements of applications can be quite diverse and consequently, resource bottlenecks or excesses can vary considerably. Thus, reconfiguration between just two core modes may not fully exploit power and performance improvement opportunities. We therefore, explore reconfigurable architectures consisting of diverse core types that not limited to big and little cores. A single core can reconfigure into multiple core modes where each mode has unique power and performance characteristics. Workload performance on a particular core mode depends on a large set of processor resources. Some workloads are highly memory intensive, some exhibit large instruction dependency, some experience high rates of branch mis-prediction, while other workloads exhibit large exploitable instruction level parallelism. A diverse set of core modes is needed, that could address shifting resource needs during various program phases of an application. Different trade-offs in power and performance could be achieved by reducing or expanding the size of various resource. Trade-offs for each core mode are also affected by operating voltage and frequency. We therefore, propose joint core resource resizing with dynamic voltage and frequency scaling (DVFS), which is important for applications whose performance is sensitive to changes in frequency. Thus, at fine granularity, the core should adapt to varying instruction window sizes, execution bandwidth and frequency to meet the demands of the workload at run-time to improve power efficiency. Many current processors employ DVFS aggressively to improve power efficiency and maximize performance. This dissertation studies the tradeoff in power efficiency in using fine grain DVFS and reconfigurable architectures mentioned above.We also explore another important problem due to continued scaling of devices which results in higher vulnerability to soft-errors. We consider dynamic core reconfiguration from the perspectives of both power efficiency and vulnerability to soft-errors. An online management scheme is proposed such that core reconfiguration upon a thread switch not only improves power efficiency but also does not increase the vulnerability to soft errors. In summary, we propose in this thesis several solutions for improving power efficiency by integrating heterogeneity within the core. We also address how popular power reduction techniques like DVFS are comparable to our approach. Finally, we address reliability challenges along with improving power efficiency.

Fil: Libman, Emiliano. Universidad de Buenos Aires. Facultad de Ciencias Económicas

Fil: Bidinost Español, Denise Solange. Universidad de Buenos Aires. Facultad de Ciencias Económicas

Tesis de Maestría El objetivo de este trabajo es brindar una explicación que dé cuenta de las razones por las cuales surge el control de cambios, sus alternativas y cuáles pueden ser algunas de sus posibles consecuencias, haciendo hincapié en el caso argentino. Fil: Gahn, Santiago José. Universidad Nacional de San Martín. Instituto de Altos Estudios Sociales; Argentina