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We introduce MiniMax-01 series, including MiniMax-Text-01 and MiniMax-VL-01, which are comparable to top-tier models while offering superior capabilities in processing longer contexts. The core lies in lightning attention and its efficient scaling. To maximize computational capacity, we integrate it with Mixture of Experts (MoE), creating a model with 32 experts and 456 billion total parameters, of which 45.9 billion are activated for each token. We develop an optimized parallel strategy and highly efficient computation-communication overlap techniques for MoE and lightning attention. This approach enables us to conduct efficient training and inference on models with hundreds of billions of parameters across contexts spanning millions of tokens. The context window of MiniMax-Text-01 can reach up to 1 million tokens during training and extrapolate to 4 million tokens during inference at an affordable cost. Our vision-language model, MiniMax-VL-01 is built through continued training with 512 billion vision-language tokens. Experiments on both standard and in-house benchmarks show that our models match the performance of state-of-the-art models like GPT-4o and Claude-3.5-Sonnet while offering 20-32 times longer context window. We publicly release MiniMax-01 at https://github.com/MiniMax-AI., Comment: A technical report from MiniMax. The authors are listed in alphabetical order. We open-sourced our MiniMax-01 at https://github.com/MiniMax-AI

Ultrathin oxide semiconductors with sub-1-nm thickness are promising building blocks for ultrascaled field-effect transistor (FET) applications due to their resilience against short-channel effects, high air stability, and potential for low-energy device operation. However, the n-type dominance of ultrathin oxide FET has hindered their integration into complementary metal-oxide-semiconductor (CMOS) technology, which requires both n-and p-type devices. Here we develop an ab initio device-driven computational screening workflow to identify sub-1-nm thickness oxide semiconductors for sub-5-nm FET applications. We demonstrate that ultrathin CaO2, CaO, and SrO are compatible with p-type device operations under both high-performance (HP) and low-power (LP) requirements specified by the International Technology Roadmap of Semiconductors (ITRS), thereby expanding the limited family of p-type oxide semiconductors. Notably, CaO and SrO emerge as the first-of-kind sub-1-nm thickness oxide semiconductors capable of simultaneously meeting the ITRS HP and LP criteria for both n-and p-type devices. CaO and SrO FETs outperform many existing low-dimensional semiconductors, exhibiting scalability below 5-nm gate length. Our findings offer a pioneering effort in the ab initio, device-driven screening of sub-1-nm thickness oxide semiconductors, significantly broadening the material candidate pool for future CMOS technology nodes., Comment: 23 pages, 5 figures, 1 table

Wide bandgap oxide semiconductors are very promising channel candidates for next-generation electronics due to their large-area manufacturing, high-quality dielectrics, low contact resistance, and low leakage current. However, the absence of ultra-short gate length (Lg) p-type transistors has restricted their application in future complementary metal-oxide-semiconductor (CMOS) integration. Inspired by the successfully grown high-hole mobility bilayer (BL) beta tellurium dioxide (\b{eta}-TeO2), we investigate the performance of sub-5-nm-Lg BL \b{eta}-TeO2 field-effect transistors (FETs) by utilizing first-principles quantum transport simulation. The distinctive anisotropy of BL \b{eta}-TeO2 yields different transport properties. In the y-direction, both the sub-5-nm-Lg n-type and p-type BL \b{eta}-TeO2 FETs can fulfill the International Technology Roadmap for Semiconductors (ITRS) criteria for high-performance (HP) devices, which are superior to the reported oxide FETs (only n-type). Remarkably, we for the first time demonstrate the existence of the NMOS and PMOS symmetry in sub-5-nm-Lg oxide semiconductor FETs. As to the x-direction, the n-type BL \b{eta}-TeO2 FETs satisfy both the ITRS HP and low-power (LP) requirements with Lg down to 3 nm. Consequently, our work shed light on the tremendous prospects of BL \b{eta}-TeO2 for CMOS application.

Graphene nanoribbon (GNR) emerges as an exceptionally promising channel candidate due to its tunable sizable bandgap (0-3 eV), ultrahigh carrier mobility (up to 4600 cm^(2) V^(-1) s^(-1)), and excellent device performance (current on-off ratio of 10^(7)). However, the asymmetry of reported n-type and p-type GNR field-effect transistors (FETs) at ultrashort gate length (Lg) has become an obstacle to future complementary metal-oxide-semiconductor (CMOS) integration. Here, we conduct ab initio quantum transport simulations to investigate the transport properties of sub-5-nm Lg 7 armchair-edge GNR (7 AGNR) FETs. The on-state current, delay time, and power dissipation of the n-type and p-type 7 AGNR FETs fulfill the International Technology Roadmap for Semiconductors targets for high-performance devices when Lg is reduced to 3 nm. Remarkably, the 7 AGNR FETs exhibit superior n-type and p-type symmetry to the 7-9-7 AGNR FETs due to the more symmetrical electron/hole effective masses. Compared to the monolayer MoS2 and MoTe2 counterparts, the 7 AGNR FETs have better device performance, which could be further improved via gate engineering. Our results shed light on the immense potential of 7 AGNR in advancing CMOS electronics beyond silicon.

Sub-1-nm gate length $MoS_2$ transistors have been experimentally fabricated, but their device performance limit remains elusive. Herein, we explore the performance limits of the sub-1-nm gate length monolayer (ML) $MoS_2$ transistors through ab initio quantum transport simulations. Our simulation results demonstrate that, through appropriate doping and dielectric engineering, the sub-1-nm devices can meet the requirement of extended 'ITRS'(International Technology Roadmap for Semiconductors) $L_g$=0.34 nm. Following device optimization, we achieve impressive maximum on-state current densities of 409 $\mu A / \mu m$ for n-type and 800 $\mu A / \mu m$ for p-type high-performance (HP) devices, while n-type and p-type low-power (LP) devices exhibit maximum on-state current densities of 75 $\mu A / \mu m$ and 187 $\mu A / \mu m$, respectively. We employed the Wentzel-Kramer-Brillouin (WKB) approximation to explain the physical mechanisms of underlap and spacer region optimization on transistor performance. The underlap and spacer regions primarily influence the transport properties of sub-1-nm transistors by respectively altering the width and body factor of the potential barriers. Compared to ML $MoS_2$ transistors with a 1 nm gate length, our sub-1-nm gate length HP and LP ML $MoS_2$ transistors exhibit lower energy-delay products. Hence the sub-1-nm gate length transistors have immense potential for driving the next generation of electronics.

Ultra-thin (UT) oxide semiconductors are promising candidates for back-end-of-line (BEOL) compatible transistors and monolithic three-dimensional integration. Experimentally, UT indium oxide (In$_2$O$_3$) field-effect transistors (FETs) with thicknesses down to 0.4 nm exhibits extremely high drain current (10000 $\mu$A/$\mu$m) and transconductance (4000 $\mu$S/$\mu$m). Here, we employ the ab initio quantum transport simulation to investigate the performance limit of sub-5-nm gate length (Lg) UT In$_2$O$_3$ FET. Based on the International Technology Roadmap for Semiconductors (ITRS) criteria for high-performance (HP) devices, the scaling limit of UT In$_2$O$_3$ FETs can reach 2 nm in terms of on-state current, delay time, and power dissipation. The wide bandgap nature of UT In$_2$O$_3$ (3.15 eV) renders it a suitable candidate for ITRS low-power (LP) electronics with Lg down to 3 nm. Both the HP and LP UT In$_2$O$_3$ FETs exhibit superior energy-delay products as compared to other common 2D semiconductors such as monolayer MoS2 and MoTe2. Our study unveils the immense promise of UT In$_2$O$_3$ for both HP and LP device applications., Comment: 16 pages, 7 figures

Gate-all-around (GAA) nanowire (NW) field-effect transistor (FET) is a promising device architecture due to its superior gate controllability than that of the conventional FinFET architecture. The significantly higher electron mobility of indium phosphide (InP) NW than silicon NW makes it particularly well-suited for high-performance (HP) electronics applications. In this work, we perform an ab initio quantum transport simulation to investigate the performance limit of sub-5-nm gate length (Lg) GAA InP NW FETs. The GAA InP NW FETs with Lg of 4 nm can meet the International Technology Roadmap for Semiconductors (ITRS) requirements for HP devices from the perspective of on-state current, delay time, and power dissipation. We also investigate the impact of strain on 3-nm-Lg GAA InP NW FETs. The application of tensile strain results in a remarkable increase of over 60% in the on-state current. These results highlight the potential of GAA InP NW FETs for HP applications in the sub-5-nm Lg region., Comment: 22 pages, 7 figures