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In this work, avalanche ruggedness and failure mechanism of SiC MOSFET in single-pulse Unclamped Inductive Switching (UIS) test are investigated and compared with Si IGBT. The experimental results show that SiC MOSFET can handle ∼20% higher avalanche energy at the same current density, and ∼50% higher current density at the same amount of energy. As SiC device has 5× smaller chip size, the advantage will disappear when comparison is performed with avalanche current. To improve the avalanche current capability of SiC MOSFET, failure mechanisms are analyzed. At first, the junction temperature is calculated with V-T model and thermal model, from which a linear dependence of temperature on avalanche current is revealed. Then, the probability of parasitic BJT turn-on is modeled analytically with the base-to-emitter resistance/voltage, which is found to be highly dependent on the p+ ohmic contact resistance (ρc) and base doping concentration (NB) designs of the device. Based on the modeling results, at the peak junction temperature 650 K in UIS test, the BJT turn-on can already be triggered for SiC MOSFET. The failure trigger temperature can be raised with a higher NB and lower ρc design, thus the avalanche current capability can be increased accordingly. On the other hand, with a much deeper p+ body structure design, the Si IGBT can prevent the BJT latch-up failure. Based on the failure analysis, a trench source structure of SiC MOSFET is proposed to further improve the avalanche capability for smaller chip size design.

In computer-controlled optical surfacing (CCOS), the paths of the lap tools are limited inside the optical surface; this restricts convolution in the dwell-time algorithm and causes mid-spatial-frequency surface errors. An optimized strategy ensuring relatively complete convolution of the dwell-time algorithm is developed to control the mid-spatial-frequency surface error and simultaneously ensure high optical manufacturing efficiency. Different-sized lap tools are then introduced to correct the surface error in different areas of the optics. Simulations and experiments using a large off-axis SiC mirror demonstrate the validity of the strategy, and it could be widely applied to CCOS in grinding or polishing processes.

Magnetorheological finishing (MRF) fabrication can effectively facilitate a rapid fabrication of an aspherical 2 m reaction-bonded silicon carbide mirror. The dwell-time algorithm and tool path supported tool-mark mitigation and virtual-axis employment are analyzed. A rapid-fabrication strategy alternates MRF and a large polishing lap to converge surface error profile before MRF alone is used to high-precise finishing. In the alternate-use process, large polishing lap’s dwell time map for low-order space frequency is calculated before MRF’s for high-order one, but executed later in reality. The fabricated mirror with a silicon modification layer showed accuracy convergence from 0.098 λ rms to 0.019 λ rms at 84.6 h, demonstrating the strategy’s validity for large optical-surface processing. Keywords: Computer controlled polishing, Silicon carbide mirror, Surface error, Magnetorheological finishing, Large polishing lap

This paper presents a high-efficiency multiple-string linear LED driver with genetic algorithm (GA) based configuration. Compared with traditional LED drivers, linear LED drivers have advantages of high efficiency, simple structure, low cost and long life-time. To achieve the high efficiency target for multiple-string linear LED driver, the configuration of LED number in each string is a great challenge. In this paper, a method based on genetic algorithm is proposed for the string LED number (i.e. string voltage) optimization. The system efficiency analysis with input voltage and LED current is introduced. And, the GA design flowchart and interface are provided. With the developed GA algorithm code, the optimal voltage for each string can be calculated. To validate the methodology, simulations are carried out to compare the GA based configuration and other four references. The results show that the GA based configuration can achieve the highest efficiency of 96%, which is >8% higher than the other configurations under the same condition.

This paper presents an instantaneous pulse power compensator (IPPC) concept to achieve ultra-high density with zero voltage ripple and zero dc-link capacitor for high-power-density single-phase inverter application. Compared with traditional 2ndorder method with various power decoupling topologies, IPPC proposed a totally new theoretical analysis from a pulse-power point of view. For dc-link voltage ripple evaluation, traditional theoretical analysis is not suitable for small-capacitance power decoupling applications, however, pulse power analysis can be applied in the whole range. From a view of state-of-the-art on power decoupling methods, a comparison figure with voltage ripple and dc-link capacitance is given to show the limitation of traditional power decoupling method and improvement of IPPC method on minimizing dc-link capacitance. One case study is presented with full-bridge topology with simulation results. Furthermore, one Silicon Carbide (SiC) based inverter and the IPPC based circuit are built. Experimental results verify the proposed idea very well.

In this work, avalanche ruggedness and failure mechanisms of 900V SiC MOSFETs under single-pulse Unclamped Inductive Switching (UIS) test are investigated and compared with Si counterparts. It was found in this work that, due to the higher resistance to BJT latch-up, only uniform heating related device temperature limit failure exists in SiC MOSFETs. Experimental results also show that, SiC MOSFETs have 9 times higher avalanche energy per area and 50% higher avalanche current than Si MOSFETs in low inductance/short pulse condition. In large inductance/long pulse condition, SiC MOSFETs have shorter avalanche duration, lower avalanche current and only similar avalanche energy per area compared to Si, due to the much smaller (15∗) chip size, thinner active layer thickness and higher power density.

In this paper, design, fabrication and experimental analysis of a novel 4H-SiC pinched barrier rectifier (PBR) are presented. The operation mechanism of the pinched barrier is analyzed by numerical simulation and energy band diagrams. PN junction depth (X j ) and spacing (S) parameters in the diode structure are carefully designed to achieve a prototype optimal structure, and both forward and reverse characteristics are compared with those of JBS diodes by experimental results. It is demonstrated that, only by simply adjusting the PN junction depth and spacing parameters, the pinched barrier diode can obtain relatively optimal performance close to that of JBS diodes. The addition of channel doping concentration (Nch) consideration for the structure design can achieve further improvements and superior performances than JBS diodes. In comparison with the optimum JBS diode design (S=1.2pm), for an on-set voltage control of 0.8V, PBR diode with optimum design sets of S and Nch can achieve a wider trade-off window (S≤0.8pm) between the device forward and reverse performances. Furthermore, PBR diode can achieve superior performance with lower forward voltage drop (1.3V) than JBS diode (1.6V) for the same reverse blocking capability (∼1600V). The performance limit of PBR diode is also explored in this paper. For a minimum limit on-set voltage control of 0.6 V, a lowest voltage drop of 1.1V as well as a wide design window can be achieved.

Praseodymium(dibenzoylmethanato)3(bathophenanthroline) [Pr(DBM)3bath] was employed as an emitting and electron transport layer, and N,N′-diphenyl-N,N′-bis(3-methylphenyl)-1, 1′-biphenyl-4,4′-diamine (TPD) as a hole transport layer in organic electroluminescent (EL) devices. Bilayer device TPD/Pr(DBM)3bath and trilayer devices TPD/TPD:Pr(DBM)3bath/Pr(DBM)3bath with a different ratio of TPD to the Pr-complex were fabricated. Emission bands at 608 nm (1D2→3H6), 890 nm (1D2→3F2), 1015 nm (1D2→3F3), 1065 nm (1D2→3F4) and 1550 nm (1D2→1G4) originating from the internal f–f transitions of a Pr3+ ion were observed from EL devices using both bilayer and trilayer structures. Decreasing the ratio of TPD to the Pr-complex, the emission of the 1D2→3H6 transition was promoted and that from the exciplex suppressed, which was explained in terms of energy transfer from the ligand to the central ion.

It is well known that the performance of Internet of Things application services is easy to be affected by internal noise of sensor, external environment interference and constriction of system resource. In order to solve the above problems, we studied the characteristics of bit error rate, outage ratio, signal to noise, and scale of relay sensors with channel state to choose the optimal transmission control scheme between direct mode and cooperative mode, building upon which we proposed the opportunistic cooperative automatic repeat request (ARQ) mechanism based on the rules and features of throughput ratio, average delay, packet error rate and energy efficiency, in consideration of retransmission time and channel quality. More importantly, the proposed opportunistic cooperative ARQ mechanism could set up the max retransmission time and control the progress of cooperative transmission according to the real-time network and sensor state, as well as Quality of Services (QoS) guarantee requirements of Internet of Things applications. The mathematical analyses and experiment results show that the proposed scheme is superior to the QoS provisioning schemes based on cooperative ARQ alone and direct transmission with channel state alone in terms of reliability, real time performance and life cycle of system, as well as energy efficiency.