Search

The High Energy Photon Source (HEPS) represents a fourth-generation light source. This facility has made unprecedented advancements in accelerator technology, necessitating the development of new detectors to satisfy physical requirements such as single-photon resolution, large dynamic range, and high frame rates. Since 2016, the Institute of High Energy Physics has introduced the first user-experimental hybrid pixel detector, progressing to the fourth-generation million-pixel detector designed for challenging conditions, with the dual-threshold single-photon detector HEPS-Beijing PIXel (HEPS-BPIX) set as the next-generation target. HEPS-BPIX will employ the entirely new Application-Specific Integrated Circuit (ASIC) BP40 for pixel information readout. Data flow will be managed and controlled through readout electronics based on a two-tier Field-Programmable Gate Array (FPGA) system: the Front-End Electronics (FEE) and the Input-Output Board (IOB) handle the fan-out for 12 ASICs, and the u4FCP is tasked with processing serial data on high-speed links, transferring pixel-level data to the back-end RTM and uTCA chassis, or independently outputting through a network port, enabling remote control of the entire detector. The new HEPS-BPIX firmware has undergone a comprehensive redesign and update to meet the electronic characteristics of the new chip and to improve the overall performance of the detector. We provide an overview of the core subunits of HEPS-BPIX, emphasizing the readout system, evaluating the new hardware and firmware, and highlighting some of its innovative features and characteristics.

The design, construction, and commissioning of a conduction-cooled Nb3Sn demonstration superconducting radio frequency (SRF) electron accelerator at the Institute of Modern Physics of the Chinese Academy of Sciences (IMP, CAS) will be presented. In the context of engineering application planning for Nb3Sn thin-film SRF cavities within the CiADS project, a 650MHz 5-cell elliptical cavity was coated using the vapor diffusion method for electron beam acceleration. Through high-precision collaborative control of 10 GM cryocooler, slow cooldown of the cavity crossing 18K is achieved accompanied by obviously characteristic magnetic flux expulsion. The horizontal test results of the liquid helium-free (LHe-free) cryomodule show that the cavity can operate steadily at Epk=6.02MV/m in continuous wave (CW) mode, and at Epk=14.90MV/m in 40% duty cycle pulse mode. The beam acceleration experiment indicates that the maximum average current of the electron beam in the macropulse after acceleration exceeds 200mA, with a maximum energy gain of 4.6MeV. The results provide a principle validation for the engineering application of Nb3Sn thin-film SRF cavities, highlighting the promising industrial application prospects of a small-scale compact Nb3Sn SRF accelerator driven by commercial cryocoolers.

The calibration process for the hybrid array pixel detector designed for High Energy Photon Source in China, we called HEPS-BPIX, is presented in this paper. Based on the threshold scanning, the relationship between energy and threshold is quantified for the threshold calibration. For the threshold trimming, the precise algorithm basing on LDAC characteristic and fast algorithm basing on LDAC scanning are proposed in this paper to study the performance of the threshold DACs which will be applied to the pixel. The threshold dispersion has been reduced from 46.28 mV without algorithm to 6.78 mV with the precise algorithm, whereas it is 7.61 mV with fast algorithm. For the temperature from 5 to 60 , the threshold dispersion of precise algorithm varies in the range of about 5.69 mV, whereas it is about 33.21 mV with the fast algorithm which can be re-corrected to 1.49 mV. The measurement results show that the fast algorithm could get the applicable threshold dispersion for a silicon pixel module and take a shorter time, while the precise algorithm could get better threshold dispersion, but time consuming. The temperature dependence of the silicon pixel module noise is also studied to assess the detector working status. The minimum detection energy can be reduced about 0.83 keV at a 20 lower temperature.

To provide the generic clock, trigger and control function and fulfill the data transmission performance requirement in high energy physics (HEP) experiments, a MicroTCA Fast Control board (uFC) was developed based on the Advanced Mezzanine Card (AMC) specification. Built around the Xilinx Kintex-7 FPGA, the uFC provides users with a platform with data memory, reference clock, trigger and SFP+ (Small Form-factor Pluggable) connections that are required in general experiment. In addition, it has access to two on-board FPGA Mezzanine Card (FMC) sockets with a large array of configurable I/O and high-speed links up to 10 Gbps. This paper presents test results from the first set of pre-production prototypes and reports on the application in High Energy Photon Source in China., Comment: 5 pages, 8 figures, proceedings of 21st IEEE Real Time Conference Colonial Williamsburg 9-15 June 2018

With the rapid development of network protocol, TCP/IP has been widely applied in various OS systems because of its advantages of high-speed network transmission and standardization. Furthermore, TCP/IP has the functions of retransmission and flow control, so it can ensure data's security and stability. In recent years, as a transmission Field-bus, it is also widely used in high-energy physics detectors. This article describes a readout method using 10 gigabit network processor applied in silicon pixel detector which is a pixel detector designed for the High Energy Photon Source (HEPS) in China. The PHY layer and the MAC layer of this hardware are both instantiated in FPGA. The logic of hardware can process and read out the data of the detectors. Meanwhile, it wraps up data and send them to TOE (TCP Offload Engine). A kind of bus control protocol interface is also provided, which can facilitate the host computer to read and write the specific register directly through the UDP protocol. Only a piece of FPGA can complete the processing of the TCP and UDP packets. It is important for the miniaturization of the detectors., Comment: 4 pages, 12 figures, proceedings of 21st IEEE Real Time Conference Colonial Williamsburg 9-15 June 2018