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A direct bidirectional current discharge path between the input/output (I/O) and ground (GND) is essential for the robust protection of charging device models (CDM) in the tightly constrained design parameters of advanced low-voltage (LV) processes. Dual-direction silicon controlled rectifiers (DDSCRs) serve as ESD protection devices with high efficiency unit area discharge, enabling bidirectional electrostatic protection. However, the high trigger voltage of conventional DDSCR makes it unsuitable for ASICs used for the preamplification of biomedical signals, which only operate at low supply voltage. To address this issue, a self-biased triggered DDSCR (STDDSCR) structure is proposed to further reduce the trigger voltage. When the ESD pulse comes, the external RC trigger circuit controls the PMOS turn-on by self-bias, and the current release path is opened in advance to reduce the trigger voltage. As the ESD pulse voltage increases, the SCR loop opens to establish positive feedback and drain the amplified current. Additionally, the junction capacitance is decreased through high-resistance epitaxy and low-concentration P-well injection to further lower the trigger voltage. The simulation results of LTspice and TCAD respectively demonstrate that ESD devices can clamp transient high voltages earlier, with low parasitic capacitance and leakage current suitable for ESD protection of high-speed ports up to 1.5 V under normal operating conditions. [ABSTRACT FROM AUTHOR]

This paper presents a compact Micro-Electro-Mechanical System (MEMS) microphone digital readout system. The system is characterized by a low-dropout regulator (LDO) and a pre-amplifier and programmable-gain amplifier (PPA)-less voltage controlled oscillator (VCO)-based Δ Σ modulation technique, which improve compactness and design scalability. Specifically, to improve signal accuracy and maintain loop stability without a gain-tuning range trade-off, an active low pass filter (ALPF) and a current mode feed-forward path (CMFFP) are incorporated in a VCO-based delta-sigma modulation loop. By means of VCOs and SCG phase variation robustness and current source array feedback (CSAFB), the system achieves a high power supply rejection ratio (PSRR) and gain tuning without the need to design an extra regulator and PPA. The design was fabricated using a 180 nm Bipolar-CMOS-DMOS (BCD) process and measured at a 1.2 V supply voltage. According to the measurement results, the signal-to-noise and distortion ratio (SNDR) achieves 62 dB@1 kHz with 40 dB gain and a 10 kHz bandwidth. Furthermore, PSRR@1 kHz is below −55 dB, and power dissipation is within 57 µW. [ABSTRACT FROM AUTHOR]

A driving amplifier capable of operating at a minimum voltage is proposed, aiming to subdue the distortion effect caused by large amplitude driving at the hearing aid loudspeaker. Since the linearity of a cascode amplifier usually degrades with the reduced supply voltage, a three-stage cascade amplifier having a parallel cascade second stage, and a folded cascade Class-AB output current control in place are designed. With such an arrangement, the open loop gain should still be maintained at a sufficiently high level even in the presence of increased output amplitude. Also, the minimum supply voltage required can then be reduced to merely | V GS | + 2 | V dsat |. Fabricated on a 0.18 μ m complementary metal oxide semiconductor (CMOS) process, the proposed amplifier achieves − 7 2 dB total harmonic distortion (THD) + noise (N) with a loudspeaker load of 100 ohm while operating from a 1.2 V supply and being subject to a 1 kHz sinusoidal input. [ABSTRACT FROM AUTHOR]

A high-PSRR low dropout regulator using the first-stage reference-included coarse-filtering technique is presented, for the reduced output ripple of the low noise block (LNB) power supply in the satellite set-top box. Compared with the conventional system, the regulator with the technique is characterized by the two successive negative feedback loops, so as to alleviate the output ripple of the power supply caused by the preceding DC-DC converter's modulation signal. With the technique, the ripple near to the frequency of the LNB supply voltage tuning signal (22 kHz) can be significantly alleviated. To further enhance the PSRR performance without the reference-by-pass capacitor, the bipolar-loop buffer amplifier and the reference-included coarse-filtering regulator are proposed. The circuits are extracted from the LDO layout and simulated with a 0.35 μm BCD process in Cadence. With the typical 16.3 V input supply voltage and loading current 100 mA, the line regulation corresponding to the DC supply voltage is achieved at -72 dB; the PSRR performance of the supply voltage ripple up to the frequency (100 kHz) is better than -70 dB; Moreover, the quiescent current without the loading impedance is less than 153 μA. [ABSTRACT FROM AUTHOR]