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The medium-voltage grid emulator is gaining popularity for testing grid-code compliance of large-capacity converters for renewable energy resources. The cascaded H-bridge converter based on active-front-ends is a promising candidate for high-power grid emulators owing to its high modularity and extendibility. However, the cascaded H-bridge topology-based grid emulator suffers the undesired and unpredictable large dc-link voltage ripple under output voltages with multiple-frequency components, e.g., when emulating the grid voltage flickers and harmonics. In this article, the dc-link voltage ripple characteristics under multi-frequency output conditions are analyzed and a dc-link ripple suppression method adopting harmonic current injection is proposed. The injected current reference is generated by reconstructing the dc-link output current and added to the original active-front-end current control loop. Compared with the existing control methods, e.g., proportional-integral-resonant (PIR), the proposed method has a good voltage ripple suppression effect, especially for multi-frequency outputs. Furthermore, the proposed idea does not need complicated calculation or extra control loops and provides a feedforward reference for the current control, leading to a good dynamic response of dc-link voltage control. Finally, the performance of this suppression control scheme is verified on two 1200 V@40 kW power electronics building blocks of a cascaded H-bridge converter.

In electric vehicle (EV) inverter systems, the dc-link capacitor bank becomes a critical obstacle to high power density due to its large volume. The dc-link capacitor bank commonly adopts a multicore parallel structure. The challenges exist in the current sharing of parallel capacitor cores because of the imbalance of stray parameters in the busbars. A current sharing analysis method aiming at thermal stress for capacitor banks in high-power-density inverters based on the characteristic matrix is proposed in this article. First, the design basis of dc-link capacitors is given theoretically. Then, the complex coupling impedance model between multiple ports on capacitor busbars is mathematically derived by the matrix method, revealing the current resonance phenomenon of parallel capacitor cores affected by stray parameters. Next, three capacitor banks are evaluated by the proposed current sharing model. The influence of capacitor core arrangement and terminal position on current sharing is explored, which can guide capacitor banks’ high-power-density structure and heat dissipation design. Finally, an experimental platform is built with customized capacitor samples. The experimental results are consistent with the analysis results of the model, verifying the proposed method.

Conventional finite control set model predictive control (FCS-MPC) for three-phase three-level (3P-3L) converters suffers from cumbersome weighting factor design, variable switching frequency, and performance compromise in neutral point potential (NPP) and current. This article proposes a modulated FCS-MPC to eliminate weighting factor, fix switching frequency, and combine NPP balance performance with current tracking performance for 3P-3L T-type converter. First, a vector synthesis algorithm with NPP deviation suppression is adopted to improve vector accuracy for current tracking, and reduce NPP deviation by redundant vector duration time adjustment. Second, a zero-sequence component injection algorithm is proposed, which determines zero-sequence component amplitude according to capacitor charge balance algorithm, and balances NPP without weighting factor. Third, a dual carrier modulation mode is adopted to produce desired switching signals with constant frequency. Finally, advantages of proposed FCS-MPC are verified by simulation and experiment.

Active neutral-point clamped three-phase five-level (3P-5L) converter system under conventional FCS-MPC algorithm is subjected to high computational burden, large common mode voltages (CMVs), unfixed switching frequency, and cumbersome weight factor design. To tackle above defects, in this article, a low computing FCS-MPC based on voltage vector tracking algorithm with CMVs suppression and capacitor charging balance algorithm without weight factors is proposed for ANPC 3P-5L converters. First, a voltage vector tracking algorithm with CMVs suppression is adopted, which filtrates 64 redundant voltage vectors to reduce CMVs, selects voltage vector by sector boundary conditions to lower computational burden, and enhances vector tracking accuracy with fixed switching frequency. Second, a capacitor charging balance algorithm is proposed to balance flying capacitor voltages (FCVs) and dc capacitor voltages (DCVs) without weight factors, which adjusts operation time of redundant switch states to balance FCVs according to each phase flying capacitor charges, and selects redundant switch states to balance DCVs according to upper and lower capacitor charges. Finally, advantages of proposed MPC are verified in experiment, where the errors of current, FCVs and DCVs are decreased by 1.4 A, 1.2 V and 0.2 V, and current THD, transient time and code execution time are decreased by 2.25%, 20 ms and 151.5 μs respectively.

In this article, a series-connected SiC MOSFETs-based medium voltage (MV) dual active bridge (DAB) converter featuring a low voltage difference among devices and high efficiency is proposed. In the developed DAB converter, the zero voltage switching-on characteristic is used to redesign the voltage balancing snubber circuits of the series-connected SiC MOSFETs. The snubber resistance is greatly reduced, whereas the snubber capacitance is increased, which realizes good voltage sharing and low switching-off loss of SiC MOSFETs. Furthermore, the operating modes and the operating characteristics of MV DAB converter with large snubber capacitors are derived in detail. Based on the above analysis, snubber capacitance and auxiliary inductance are optimized, taking into account the losses and voltage imbalance in the series-connected SiC MOSFETs. Finally, a 4 kV/1 kV experimental prototype is built and tested, and an experiment with up to 100 kW transmission power has been carried out. The results show that a maximum efficiency of 98.7% has been reached and the maximum voltage difference among SiC MOSFETs does not exceed 4%.

Medium voltage high-frequency transformer (MVHFT), the key component in a MV solid-state transformer (MVSST), requires high reliability on its insulation parts. With the increase of power density, the insulation design of the MVHFT becomes a big challenge. The transformer needs to ensure both high breakdown (BD) strength for short-term fault tolerance and low partial discharge (PD) for long-term reliable operation. Therefore, beginning with the electric stress analysis and the anti-corona consideration, a mass-manufacturable insulation structure is proposed in this article. In the structure, an improved multishielding structure with an optimized shield potential design is used to reshape the electric field (E-field) distribution for higher BD strength and lower PD. And an end-winding stress grading (SG) method is proposed and modeled for both the structure and the material used. Finally, with the proposed insulation structure, a 100 kW PD free transformer prototype with 75 kV base insulation level (BIL) is built. It passed all insulation tests. Also, the prototype realizes high power density under a high insulation level, which reaches 11.2 kW/L.