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18 results on '"Lekashri, S."'

10. Adaptive real-time reconfiguration gate scheduling scheme using time perceptive stream

Author

Lekashri, S., Madhusudhan, K. N., SivaSangari, A., Gururama Senthilvel, P., Lekashri, S., Madhusudhan, K. N., SivaSangari, A., and Gururama Senthilvel, P.

Abstract

An adaptive real-time gate scheduling scheme for time perceptive stream or packet flow is proposed to improve the standards of Ultra Low Latency during data transmission. For highly dynamic network conditions, the conventional configuration scheme is not suitable and therefore an adaptive real-time gate scheduling method is proposed for time perceptive streams. This dynamicity reconfiguration is difficult and the scheduling problem is formulated using Field Programmable Gate Array – Boolean Satisfiability Problem (FPGA-BSP) solver. This proposed scheme highly helps in network dynamicity conditions with good bandwidth utilization and high flexibility. End-to-end latency is required to be on sub-milliseconds order deal with the applications such as Industrial Internet of Things, 5G and 6G mobile, tactile internet and so on. Simulation analysis is carried out to prove the efficiency of the proposed model.

Published
2023

11. Effective task scheduling based on interactive autodidactic school algorithm for cloud computing.

Author

Senthilkumar, G., Suvarnamukhi, B., Lekashri, S., and Thaha, M. Mohammed

Subjects
CLOUD computing, METAHEURISTIC algorithms, OPTIMIZATION algorithms, SWARM intelligence, RESOURCE allocation, SCHEDULING
Abstract

The topic of load balanced task scheduling has emerged as a prominent and intricate area of study within the realm of Cloud computing. Swarm intelligence-based meta-heuristic algorithms are commonly considered more suitable for the purposes of Cloud scheduling and load balancing. These algorithms employ a combination of local and global search strategies in order to ascertain the ideal location. To achieve an optimal mapping strategy for task allocation to resources, it is imperative to find a suitable equilibrium between local and global search techniques, since this approach has demonstrated significant efficacy. This research introduces a new approach to task scheduling using the Autodidactic Interactive School Optimization Algorithm (IASOA). The objective of this method is to decrease the time required for job execution while also enhancing throughput. The assessment of the suggested methodology has been executed, and a comparative analysis has been performed with five established algorithms in relation to makespan and throughput. The tests were subsequently extended to encompass a comparative analysis of the suggested methodology alongside four other established meta-heuristic scheduling methodologies. The study of the simulated experimentation reveals that the proposed approach yielded noteworthy advantages in makespan and throughput, with improvements of up to 10% and 60% respectively. [ABSTRACT FROM AUTHOR]

Published
2024
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18. FPTA Based Active Reconfigurable System With Configurable Margin Examine Circuit – Applications

Author

Lekashri S, Gokul C, and Sakthivel P

Subjects
Artificial neural network, business.industry, Computer science, media_common.quotation_subject, Control reconfiguration, Encryption, Field programmable transistor array, Margin (machine learning), Embedded system, Key (cryptography), Quality (business), Static random-access memory, business, media_common
Abstract

Active reconfiguration framework enables us to powerfully distribute equipment assets as required by specific applications. Field Programmable Transistor Array (FPTA) based active reconfiguration system (ARS) with Configurable Margin-Examine Circuit (CMSC) that can be applied over numerous fields like military and aircraft applications, neural network operations, artificial intelligence and so on. As a rule, if a significant capacity, for example, key encryption should be changed in ARS working on a high security framework; the comparing rationale assets should be checked and tried again before getting reconfigured. By utilizing the CMSC innovation, the powerful speed of shortcoming analysis for FPTA gets quickened, and the unwavering quality active RS will be improved. Initial stage of PCB-level can be utilized as a typical stage for static RAM_FPTA that has planned with BQV arrangement FPTA of microelectronics method BMTI. Checked with test vectors of BQV600, the total testing time for rationale assets of BQV600 has been diminished essentially.

Published
2019
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