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Large power consumption of silicon CMOS electronics is a challenge in very-large-scale integrated circuits and a major roadblock to fault-tolerant quantum computation. Matching the power dissipation of Si-MOSFETs to the thermal budget at deep cryogenic temperatures, below 1 K, requires switching performance beyond levels facilitated by currently available CMOS technologies. We have manufactured fully depleted silicon-on-insulator MOSFETs tailored for overcoming the power dissipation barrier towards sub-1 K applications. With these cryo-optimized transistors we achieve a major milestone of reaching subthreshold swing of 0.3 mV/dec at 420 mK, thereby enabling very-large-scale integration of cryo-CMOS electronics for ultra-low temperature applications.

We demonstrate ion irradiation by argon or gallium as a wafer-scale post-processing method to increase disorder in superconducting thin films. We study several widely used superconductors, both single-elements and compounds. We show that ion irradiation increases normal-state resistivity in all our films, which is expected to enable tuning their superconducting properties, for example, toward higher kinetic inductance. We observe an increase of superconducting transition temperature for Al and MoSi, and a decrease for Nb, NbN, and TiN. In MoSi, ion irradiation also improves the mixing of the two materials. We demonstrate fabrication of an amorphous and homogeneous film of MoSi with uniform thickness, which is promising, e.g., for superconducting nanowire single-photon detectors.

Cryogenic microsystems that utilize different 3D integration techniques are being actively developed, e.g., for the needs of quantum technologies. 3D integration can introduce opportunities and challenges to the thermal management of low temperature devices. In this work, we investigate sub-1 K inter-chip thermal resistance of a flip-chip bonded assembly, where two silicon chips are interconnected by compression bonding via indium bumps. The total thermal contact area between the chips is 0.306 mm$^2$ and we find that the temperature dependence of the inter-chip thermal resistance follows the power law of $\alpha T^{-3}$, with $\alpha = 7.7-15.4$ K$^4$$\mu$m$^2$/nW. The $T^{-3}$ relation indicates phononic interfacial thermal resistance, which is supported by the vanishing contribution of the electrons to the thermal conduction, due to the superconducting interconnections. Such a thermal resistance value can introduce a thermalization bottleneck in particular at cryogenic temperatures. This can be detrimental for some applications, yet it can also be harnessed. We provide an example of both cases by estimating the parasitic overheating of a cryogenic flip-chip assembly operated under various heat loads as well as simulate the performance of solid-state junction microrefrigerators utilizing the observed thermal isolation., Comment: 6 pages, 4 figures, 1 table

Owing to the maturity of complementary metal oxide semiconductor (CMOS) microelectronics, qubits realized with spins in silicon quantum dots (QDs) are considered among the most promising technologies for building scalable quantum computers. For this goal, ultra-low-power on-chip cryogenic CMOS (cryo-CMOS) electronics for control, read-out, and interfacing of the qubits is an important milestone. We report on-chip interfacing of tunable electron and hole QDs by a 64-channel cryo-CMOS multiplexer with less-than-detectable static power dissipation. We analyze charge noise and measure state-of-the-art addition energies and gate lever arm parameters in the QDs. We correlate low noise in QDs and sharp turn-on characteristics in cryogenic transistors, both fabricated with the same gate stack. Finally, we demonstrate that our hybrid quantum-CMOS technology provides a route to scalable interfacing of a large number of QD devices, enabling, for example, variability analysis and QD qubit geometry optimization, which are prerequisites for building large-scale silicon-based quantum computers., Comment: accepted manuscript; 5 figures, 18 supplementary figures, and 1 table in supplementary materials

Rapid miniaturization of electronic devices and circuits demands profound understanding of fluctuation phenomena at the nanoscale. Superconducting nanowires -- serving as important building blocks for such devices -- may seriously suffer from fluctuations which tend to destroy long-range order and suppress superconductivity. In particular, quantum phase slips (QPS) proliferating at low temperatures may turn a quasi-one-dimensional superconductor into a resistor or an insulator. Here, we introduce a physical concept of QPS-controlled localization of Cooper pairs that may occur even in uniform nanowires without any dielectric barriers being a fundamental manifestation of the flux-charge duality in superconductors. We demonstrate -- both experimentally and theoretically -- that deep in the "insulating" state such nanowires actually exhibit non-trivial superposition of superconductivity and weak Coulomb blockade of Cooper pairs generated by quantum tunneling of magnetic fluxons across the wire., Comment: 7+2 pages,5+2 figures

We report on ambipolar gate-defined quantum dots in silicon on insulator (SOI) nanowires fabricated using a customised complementary metal-oxide-semiconductor (CMOS) process. The ambipolarity was achieved by extending a gate over an intrinsic silicon channel to both highly doped n-type and p-type terminals. We utilise the ability to supply ambipolar carrier reservoirs to the silicon channel to demonstrate an ability to reconfigurably define, with the same electrodes, double quantum dots with either holes or electrons. We use gate-based reflectometry to sense the inter-dot charge transition(IDT) of both electron and hole double quantum dots, achieving a minimum integration time of 160(100) $\mu$s for electrons (holes). Our results present the opportunity to combine, in a single device, the long coherence times of electron spins with the electrically controllable holes spins in silicon., Comment: 5 pages, 4 figures

Control of heat flux at small length scales is crucial for numerous solid-state devices and systems. In addition to the thermal management of information and communication devices the mastering of heat transfer channels down to the nanoscale also enable, e.g., new memory concepts, high sensitivity detectors and sensors, energy harvesters and compact solid-state refrigerators. Electronic coolers and thermal detectors for electromagnetic radiation, especially, rely on the maximization of electro-thermal response and blockade of phonon transport. In this work, we propose and demonstrate that efficient electro-thermal operation and phonon transfer blocking can be achieved in a single solid-state thermionic junction. Our experimental demonstration relies on suspended semiconductor-superconductor junctions where the electro-thermal response arises from the superconducting energy gap, and the phonon blocking naturally results from the transmission bottleneck at the junction. We suspend different size degenerately doped silicon chips (up to macroscopic scale) directly from the junctions and cool these by biasing the junctions. The electronic cooling operation characteristics are accompanied by measurement and analysis of the thermal resistance components in the structures indicating the operation principle of phonon blocking in the junctions.