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This investigation demonstrates a 10-bit SAR-ADC with low power dissipation per conversion step at 50 MS/s sampling rate. The proposed ADC is featured with the split-capacitance array by using unity-gain amplifiers and designed for fibre optic gyroscope (FOG) systems. The buffers based on the unity-gain amplifiers replace the bridge capacitors of the split-capacitance array in conventional SAR ADCs to resist process variation and enhance linearity of the capacitor-array. Aside from those, improvements in time response, that is, settling time, and capacitor size have also been proved. The design was implemented using a typical 40-nm CMOS process. The INL (integral non-linearity) and the DNL (differential non-linearity) were found to be 0.56 LSB and 0.51 LSB, respectively. The SNDR and SFDR are 51.23 dB and 61.46 dB, respectively, at an input of 12.5 MHz showing ENOB to be 9.79 bits at a sampling rate of 50 MS/s. [ABSTRACT FROM AUTHOR]

A 5.0/3.3/1.8-V tolerant I/O buffer implemented using typical CMOS 2P4M 0.35-[micro]m process is proposed in this paper. Unlike traditional mixed-voltage-tolerant I/O buffers, the proposed I/O buffer can transmit and receive signals with voltage levels of 5.0/3.3/1.8 V. By using a stacked PMOS and a stacked NMOS at the output stage and a dynamic gate bias generator providing appropriate control voltages for the gates of the stacked PMOS, gate-oxide overstress and hot-carrier degradation are avoided. Moreover, gate-tracking and floating n-well circuits are used to remove undesirable leakage current paths. The proposed topology can be applied to any technologies with the constraint ofVDD < VDDH < 2 x VDD, which should be considered carefully in sub-100-nm technologies. Measurement results on silicon verify the function and the gate-oxide reliability of the proposed I/O buffer. The maximum transmitting speed of the proposed I/O buffer is measured to be 80/120/84 Mb/s for the supply voltage of I/O buffer at 5.0/3.3/1.8 V, respectively, given the load of 29 pF. Index Terms--Floating n-well, fully mixed-voltage-tolerant, gate-tracking, I/O buffer, level converter.

An all-MOS linear voltage-to-frequency converter (VFC) chip with 520-kHz/V sensitivity is presented in this paper. This circuit converts an input voltage into frequency by charging and discharging a capacitor. An all-MOS voltage window comparator (VWC) with reduced propagation delay is designed to improve the linearity of traditional VFCs. The propagation delay of the VWC is discussed to resolve the tradeoff between bandwidth and linearity of V-FC. The proposed VFC is verified on silicon using the Taiwan Semiconductor Manufacturing Company 1P5M 0.25-[micro]m process. The measurement results show that the linearity error is less than 1%, and the sensitivity is 520 kHz/V at an input voltage range from 0.1 to 0.8 V. Index Terms--Linearity, sensitivity, voltage window comparator (VWC), voltage-to-frequency converter (VFC).

An impedance read-out circuit with high accuracy implemented using a TSMC 0.18 um mixed-signal CMOS process for BIA-type (bio-electrical impedance analysis) sensors to detect biomarkers is proposed in this investigation. In addition to proposing the impedance estimation circuit, the associated analytic proof is also disclosed. Using a high-order approximation model and high noise rejection capability by the addition of OPAs (operational amplifiers), the proposed system demonstrates a solution with high accuracy in terms of the maximum impedance error (< 6 %) and the least phase error (< 3 ∘ ) in a frequency range from 1 kHz to 2 MHz. [ABSTRACT FROM AUTHOR]