20 results on '"Lee, Hyunbae"'
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2. Deep learning-assisted microstructural analysis of Ni/YSZ anode composites for solid oxide fuel cells
3. A 24.1 TOPS/W mixed-signal BNN processor in 28-nm CMOS.
4. A 24.1 TOPS/W mixed-signal BNN processor in 28-nm CMOS
5. Numerical Analysis of Sloshing Effects in Cryogenic Liquefied-Hydrogen Storage Tanks for Trains Under Various Vibration Conditions
6. Numerical Investigation of the Initial Charging Process of the Liquid Hydrogen Tank for Vehicles
7. Numerical Investigation of the Initial Charging Process of the Liquid Hydrogen Tank for Vehicles.
8. Three-Dimensional Printing of Natural Materials Involving Loess-Based Composite Materials Designed for Ecofriendly Applications
9. A 12-b 2 MS/s R-C Two-Step SAR ADC with Bit-Cycling Time Control and LSB Correction Logic
10. A Genome-Wide Analysis of the Pentatricopeptide Repeat (PPR) Gene Family and PPR-Derived Markers for Flesh Color in Watermelon (Citrullus lanatus)
11. All-digital half-rate referenceless CDR with single direction frequency sweep scheme using asymmetric binary phase detector
12. Application of Water-Dispersed Quantum Dots to Crack Monitoring in Smart Composite Materials
13. Application of Multipoint Impedence Spectroscopy to Corrosion Monitoring on Shape Memory Alloys in Smart Building Materials.
14. Application of Atomic Layer Deposition of Cellulosic Materials Prepared Using 3D Printing Concepts
15. Electrical/Mechanical Monitoring of Shape Memory Alloy Reinforcing Fibers Obtained by Pullout Tests in SMA/Cement Composite Materials
16. A Delay Locked Loop With a Feedback Edge Combiner of Duty-Cycle Corrector With a 20%–80% Input Duty Cycle for SDRAMs
17. A 16.8 Gbps/Channel Single-Ended Transceiver in 65 nm CMOS for SiP-Based DRAM Interface on Si-Carrier Channel
18. A 16.8Gbps/channel single-ended transceiver in 65nm CMOS for SiP based DRAM interface on Si-carrier channel
19. An 80 mV-Swing Single-Ended Duobinary Transceiver With a TIA RX Termination for the Point-to-Point DRAM Interface
20. A 27% reduction in transceiver power for single-ended point-to-point DRAM interface with the termination resistance of 4×Z0 at both TX and RX.
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