Search

Your search keyword '"Lauwereins, R."' showing total 261 results
Start Over Author "Lauwereins, R."
261 results on '"Lauwereins, R."'

1. Memory Hierarchy Energy Cost of a Direct Filtering Implementation of the Wavelet Transform

Author

Geelen, Bert, Lafruit, Gauthier, Ferentinos, V., Lauwereins, R., Verkest, Diederik, Hutchison, David, editor, Kanade, Takeo, editor, Kittler, Josef, editor, Kleinberg, Jon M., editor, Mattern, Friedemann, editor, Mitchell, John C., editor, Naor, Moni, editor, Nierstrasz, Oscar, editor, Pandu Rangan, C., editor, Steffen, Bernhard, editor, Sudan, Madhu, editor, Terzopoulos, Demetri, editor, Tygar, Dough, editor, Vardi, Moshe Y., editor, Weikum, Gerhard, editor, Paliouras, Vassilis, editor, Vounckx, Johan, editor, and Verkest, Diederik, editor

Published
2005
Full Text
View/download PDF

3. Network-on-Chip for Reconfigurable Systems: From High-Level Design Down to Implementation

Author

Bartic, T. A., Desmet, D., Mignolet, J-Y., Marescaux, T., Verkest, D., Vernalde, S., Lauwereins, R., Miller, J., Robert, F., Hutchison, David, editor, Kanade, Takeo, editor, Kittler, Josef, editor, Kleinberg, Jon M., editor, Mattern, Friedemann, editor, Mitchell, John C., editor, Naor, Moni, editor, Nierstrasz, Oscar, editor, Pandu Rangan, C., editor, Steffen, Bernhard, editor, Sudan, Madhu, editor, Terzopoulos, Demetri, editor, Tygar, Dough, editor, Vardi, Moshe Y., editor, Weikum, Gerhard, editor, Becker, Jürgen, editor, Platzner, Marco, editor, and Vernalde, Serge, editor

Published
2004
Full Text
View/download PDF

4. Design-Time Data-Access Analysis for Parallel Java Programs with Shared-Memory Communication Model

Author

Stahl, R., Catthoor, F., Lauwereins, R., Verkest, D., Hutchison, David, editor, Kanade, Takeo, editor, Kittler, Josef, editor, Kleinberg, Jon M., editor, Mattern, Friedemann, editor, Mitchell, John C., editor, Naor, Moni, editor, Nierstrasz, Oscar, editor, Pandu Rangan, C., editor, Steffen, Bernhard, editor, Sudan, Madhu, editor, Terzopoulos, Demetri, editor, Tygar, Dough, editor, Vardi, Moshe Y., editor, Weikum, Gerhard, editor, Danelutto, Marco, editor, Vanneschi, Marco, editor, and Laforenza, Domenico, editor

Published
2004
Full Text
View/download PDF

16. SOT-MRAM Based Analog in-Memory Computing for DNN Inference

Author

Doevenspeck, J., primary, Garello, K., additional, Verhoef, B., additional, Degraeve, R., additional, Van Beek, S., additional, Crotti, D., additional, Yasin, F., additional, Couet, S., additional, Jayakumar, G., additional, Papistas, I. A, additional, Debacker, P., additional, Lauwereins, R., additional, Dehaene, W., additional, Kar, G. S., additional, Cosemans, S., additional, Mallik, A., additional, and Verkest, D., additional

Published
2020
Full Text
View/download PDF

31. Design and simulation of plasmonic interference-based majority gate.

Author

Raghavan, P., Doevenspeck, Jonas, Zografos, Odysseas, Gurunarayanan, Surya, Lauwereins, R., and Sorée, B.

Subjects
COMPLEMENTARY metal oxide semiconductors, SURFACE plasmons, ELECTRONIC circuit design
Abstract

Major obstacles in current CMOS technology, such as the interconnect bottleneck and thermal heat management, can be overcome by employing subwavelength-scaled light in plasmonic waveguides and devices. In this work, a plasmonic structure that implements the majority (MAJ) gate function is designed and thoroughly studied through simulations. The structure consists of three merging waveguides, serving as the MAJ gate inputs. The information of the logic signals is encoded in the phase of transmitted surface plasmon polaritons (SPP). SPPs are excited at all three inputs and the phase of the output SPP is determined by theMAJof the input phases. The operating dimensions are identified and the functionality is verified for all input combinations. This is the first reported simulation of a plasmonic MAJ gate and thus contributes to the field of optical computing at the nanoscale. [ABSTRACT FROM AUTHOR]

Published
2017
Full Text
View/download PDF

36. Hierarchical run-time reconfiguration managed by an operating system for reconfigurable systems

Author

Nollet, V., Mignolet, J.Y., Bartic, T.A., Verkest, D., Vernalde, S., and Lauwereins, R.

Subjects
Computer. Automation, Hardware_ARITHMETICANDLOGICSTRUCTURES
Abstract

The need for flexible computational power has motivated many researchers to incorporate run-time reconfigurable logic into their architectures. Most contemporary experiments include commercial FPGA's serving as reconfigurable hardware. Unfortunately, the FPGA does not exhibit the same run-time flexibility as the Instruction Set Processor (ISP) e.g. when it comes to ease and speed of setting tip a task. In addition, FPGA's tend to be less suited than traditional ISP's to accommodate control-flow dominated tasks. Obviously, it is possible to alleviate some of these issues by using a reconfiguration hierarchy (e.g. placing and configuring an ASIP or coarse grain reconfigurable block into the FPGA). This paper illustrates how our operating system transparently manages the complexin, of hierarchical reconfiguration. In addition, this paper highlights the benefits and drawbacks of employing multiple hierarchical levels of configuration. As a proof of concept, we developed a filtering application on top of an in-house 16 bit micro-controller and a parameterizable filter block, both instantiated inside an FPGA.

Published
2003

38. Industrial embedded HPC applications

Author

Deconinck, G., Varvarigou, T., Botti, O., Florio, V. De, Kontizas, A., Truyens, M., Rosseel, W., Lauwereins, R., Cassinari, F., Graeber, S., and Knaak, U.

Published
1997

44. Caution ahead

Author

Turnoy, S, primary, Wintermayr, P, additional, Aitken, R, additional, Lauwereins, R, additional, Weed, J Tracy, additional, Kiefer, V, additional, and Hartmann, J, additional

Published
2008
Full Text
View/download PDF

Catalog

Books, media, physical & digital resources
See catalog results