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To understand how anesthetics with different molecular mechanisms affect consciousness, we explored subjective experiences recalled after responsive and unresponsive sedation induced with equisedative doses of dexmedetomidine, propofol, sevoflurane, and S-ketamine in healthy male participants (N = 140). The anesthetics were administered in experimental setting using target-controlled infusion or vapouriser for one hour. Interviews conducted after anesthetic administration revealed that 46.9% (n = 46) of arousable participants (n = 98) reported experiences, most frequently dreaming or memory incorporation of the setting. Participants receiving dexmedetomidine reported experiences most often while S-ketamine induced the most multimodal experiences. Responsiveness at the end of anesthetic administration did not affect the prevalence or content of reported experiences. These results demonstrate that subjective experiences during responsive and unresponsive sedation are common and anesthetic agents with different molecular mechanisms of action may have different effects on the prevalence and complexity of the experiences, albeit in the present sample the differences between drugs were minute. CC BY 4.0© 2021 The AuthorsCorresponding author. E-mail address: liemra@utu.fi (L. Radek).

Shown here is an analysis algorithm targeted for near-threshold ultra-wide Dynamic Voltage and Frequency Scaling (UW-DVFS) embedded systems. The algorithm defines execution frequencies based on the software execution trace. Task execution profiling and constraints are used to form a linear optimization problem. Execution frequencies are defined based on the optimization result, the DVFS scaling factors. The system’s DVFS overhead is measured and included in the model. The analyzed code is tested on a near-threshold ARM CortexM3 core with integrated PLL and power management. In this case, over 49% energy savings can be achieved for industry-standard speech-recognition software without any penalty in application throughput.

An adaptive ARM Cortex-M3 with near-threshold to nominal voltage operation is presented. Using in-situ monitoring technology, the CPU energy is minimized across process, voltage, temperature, and applications. At the Minimum-Energy Point (MEP), the CPU achieves 2.87pJ/cycle (7.8MHz/0.378V). Absolute energy consumption is reduced by 76% by operating at the MEP. The core includes a novel configuration of industry-standard ATPG-compatible DFT architecture for adaptive logic testing and the system includes Dynamic Voltage and Frequency Scaling software. Additionally presented is an execution-frequency analysis algorithm based on software execution trace. The algorithm achieves 60% energy savings for an industry-standard speech-recognition software without any penalty in application throughput.

To achieve energy efficiency in the Internet-of-Things (IoT), more intelligence is required in the wireless IoT nodes. Otherwise, the energy required by the wireless communication of raw sensor data will prohibit battery lifetime, the backbone of IoT. One option to achive this intelligence is to implement a variety of machine learning algorithms on the IoT sensor instead of the cloud. Shown here is sub-milliwatt machine learning accelerator operating at the Ultra-Low Voltage Minimum-Energy Point. The accelerator is a Transport Triggered Architecture (TTA) Application-Specific Instruction-Set Processor (ASIP) targeted for running various Machine Learning algorithms. The ASIP is implemented in 28nm FDSOI (Fully Depleted Silicon On Insulator) CMOS process, with an operating voltage of 0.35V, and is capable of 5.3pJ/cycle and 1.8nJ/iteration when performing conventional machine learning algorithms. The ASIP also includes hardware and compiler support for approximate computing. With the machine learning algorithms, computing approximately brings a maximum of 4.7% energy savings.

Timing-error-detection (TED)-based systems have been shown to reduce power consumption or increase yield due to reduced margins. This paper shows that the increased adaptability can be a great advantage in the system design in addition to the well-known mitigated susceptibility to ambient and internal variations. Specifically, the design tolerances of the power management are relaxed to enable even greater system-level energy savings than what can be achieved in the logic alone. In addition, the system is simultaneously able to operate near the minimum error point. Here, the power management is a simplified DC-DC converter and the TED is based on time borrowing. The target application is a single-chip system on chip without external discrete components; thus, switched capacitors are used for the DC-DC. The system achieves 7.9% energy reduction at the minimum energy point simultaneously with a 36.4% energy-delay product decrease and a 15% increase in DC-DC efficiency. In addition, the effect of local variations on average system performance is reduced by 12%.

With the ever increasing number of IoT devices, security and energy efficiency have become critical constraints in circuit design. To achieve small size and energy efficiency, devices need to be supplied by on-chip regulators. The power line generates the strongest signal in the circuit, and it is exploited for both, power and electromagnetic, side-channel attacks. In this work we propose to improve the security of the on-chip switched capacitor DC-DC converters by randomly switching between different converter topologies. Random ripple size and maximum supply voltage modulate the circuit current and power consumption, making the circuit more robust against side-channel attacks. We analyze the most common converter topologies and propose reconfigurable switched-capacitor cell for the efficient implementation in CMOS technology. The results show that power and time entropy of the proposed cell are increased significantly when compared to the commonly used DC-DC converter cell. There is around 6% variation in the DC-DC switching frequency for the constant load, and additional noise is observed in the frequency spectrum of the measured signal, thus, increasing the difficulty of the attack.

In memristive stateful logic memristors store logic values as their memristance states and perform logical operations on them. This form of logic has been studied intensively since it was first empirically demonstrated in the work of Borghetti , 2010. It has been previously noted that substantial parallelism in stateful computation is required to make this form of logic competetive with conventional logic computing paradigms. In this work we show how a certain class of vectorized recursive algorithms can be computed in a semiconductor/memristor hybrid array structure. This class of algorithms allows efficient computation of many practically important vector operations; examples considered in this paper include the binary sum of vectors, the parity of a vector, and the Hamming weight of a vector. We present theoretical analysis of the time and space complexity of this class of operations, and show examples of this computing method using circuit-level simulations. We also discuss possible applications of these operations in massively parallel memristive array computing.

We present a cellular memristive stateful logic computing architecture and demonstrate its operation with computational examples such as vectorized XOR, circular shift, and content-addressable memory. The considered architecture can perform parallel elementary memristor programming and stateful logic operations, namely implication and converse nonimplication. The topology of the crossbar structure used for computing can be dynamically reconfigured, enabling combinations of local and global operations with varying granularity. In the CMOS cells used for controlling the memristors, we apply a new type of capacitive keeper circuit, which allows for energy efficient implementation of logic operations. The correct operation of this architecture is verified by detailed HSPICE simulations for a structure containing eight memristive crossbars. This work presents a hardware platform which enables future work on parallel stateful computing.

The Von Neumann bottleneck originates from the low bandwidth between processing and memory. One paradigm that could ease the bottleneck is Computing-in-Memory (CiM), where the same elements store logic values and perform logical operations on them in the same physical location. Here, presented are implementations of the K-means clustering algorithm on a Memristive Logic Array-based CiM implementation and a Machine Learning specific Transport-Triggered Architecture (TTA) processor implemented on 28nm FDSOI technology and operating at 0.35V. While running K-means, the Memristive CiM is 5,7 times faster and uses 2,3 times less energy than the TTA processor. However, the average power consumption of the MLA is 2,5 times the power of the TTA.

The importance of energy-constrained processors continues to grow especially for ultra-portable sensor-based platforms for the Internet-of-Things (IoT). Processors for these IoT applications primarily operate at near-threshold (NT) voltages and have multiple power modes. Achieving high conversion efficiency within the DC–DC converter that supplies these processors is critical since energy consumption of the DC–DC/processor system is proportional to the DC–DC converter efficiency. The DC–DC converter must maintain high efficiency over a large load range generated from the multiple power modes of the processor. This paper presents a fully integrated step-down self-oscillating switched-capacitor DC–DC converter that is capable of meeting these challenges. The area of the converter is 0.0104 mm2 and is designed in 28 nm ultra-thin body and buried oxide fully-depleted SOI (UTBB FD-SOI). Back-gate biasing within FD-SOI is utilized to increase the load power range of the converter. With an input of 1 V and output of 460 mV, measurements of the converter show a minimum efficiency of 75% for 79 nW to 200 µW loads. Measurements with an off-chip NT processor load show efficiency up to 86%. The converter’s large load power range and high efficiency make it an excellent fit for energy-constrained processors.

In this paper, a micropower interface IC for a capacitive 3-axis micro-accelerometer is presented. The IC is implemented in a 0.25-mum CMOS process. The fully-integrated sensor interface is based on a DeltaSigma sensor front-end that operates mechanically in an open-loop configuration and converts the acceleration signals directly into the digital domain, thus avoiding the use of separate analog-to-digital converters. A detailed analysis with transfer functions is presented for the front-end circuit. Furthermore, the interface IC includes a decimator, a frequency reference, a clock generator for the front-end, a voltage and current reference, the required reference buffers, and low-dropout regulators (LDOs) needed for system-on-chip power management. The interface IC provides operating modes with 12-bit resolution for 1 and 25 Hz signal bandwidths. The former is optimized for very low power dissipation at the cost of reduced bandwidth, and is intended for example for activity monitoring in otherwise powered-off devices. The chip, with a 1.73 mm2 active area, draws typically 21.2 muA in the 1 Hz mode, and 97.6 muA in the 25 Hz mode, from a 1.2-2.75 V supply. In the 1 and 25 Hz modes with a plusmn 4-g capacitive 3-axis accelerometer, the measured noise floors in the x-, y-, and z-directions are 1080, 1100 and 930 mug/radic{Hz}, and 360, 320 and 275 mug/radic{Hz} , respectively. The implemented prototype achieves competitive figures of merit (FOMs) compared to the other published or commercially available, low-g, low-power accelerometers.

Due to power consumption restrictions, low-power H.264 encoders cannot take advantage of the variable block sizes available in H.264 motion estimation. This work presents two methods to determine a block-size partition without an initial search. With both of these methods, computationally burdensome Lagrange optimization is not required. The methods are derived from a cellular nonlinear network (CNN) segmentation algorithm and, along with the partition, indicate early termination of motion estimation and the skip modes of H.264. Both methods achieve better rate-distortion performance when compared to motion estimation with only 16x16 sized blocks. The 16x16 only case is descriptive of a low-power case where the variable block sizes cannot be used. For low bitrates, both methods achieve equivalent performance when compared to Lagrange optimization. Also presented are the computational complexity of the methods and the power consumption when implemented with existing CNN hardware.

FDSOI has been shown to achieve extremely high performance at low operating voltages: a use-case extremely well suited for applications such as mobile processing. In IoT and Dark Silicon, use cases with extremely low application active times per standby times can be found. Investigated here are the turnover points where the higher threshold voltage and longer channel length options of FDSOI should be used. It was found that for activity factors below 3.2% to 0.5%, depending on the voltage, the Regular V T option of FDSOI should be used.

In this paper, we present an implementation of the K-means clustering algorithm using a CMOS/memristor hybrid architecture. We verify the correctness and estimate the energy and power consumption of our implementation using HSPICE simulations.

To minimize energy consumption of a digital circuit, logic can be operated at sub- or near-threshold voltage. Operation at this region is challenging due to device and environment variations, and resulting performance may not be adequate to all applications. This article presents two variants of a 32-bit RISC CPU targeted for near-threshold voltage. Both CPUs are placed on the same die and manufactured in 28 nm CMOS process. They employ timing-error prevention with clock stretching to enable operation with minimal safety margins while maximizing performance and energy efficiency at a given operating point. Measurements show minimum energy of 3.15 pJ/cyc at 400 mV, which corresponds to 39% energy saving compared to operation based on static signoff timing. © 2015 by the authors; licensee MDPI, Basel, Switzerland.

We introduce an ultra-low-energy system comprised of a prototype 1.55V Li-ion battery, fully integrated switched-capacitor (SC) DC-DC 3:1 converter, and a 32-bit RISC CPU with timing-error prevention (TEP). The DC-DC converter and CPU are manufactured in 28nm UTBB FD-SOI. The DC-DC converter uses the battery's flat discharge curve and low nominal voltage to achieve a peak efficiency of 85%. The CPU operates from 0.3V-0.5V and with energy as low as 4.9pJ/cyc. The battery, DC-DC converter, and CPU system is able to operate with an average energy of 8pJ/cyc over 95% of the battery's discharge curve in the temperature range of −20oC to 70oC.

We introduce a fully integrated step-down self-oscillating switched-capacitor DC-DC converter that delivers near-threshold (NT) output voltages. The converter is built in 28 nm UTBB FD-SOI and occupies 0.0104 mm2. Back-gate biasing is utilized to increase the load power range. Measurements show a peak efficiency of 87%, self start-up capability, and a minimum efficiency of 75% for 79 nW to 200 μW (ideal) loads. Measurements with an off-chip NT processor load also show high efficiency. The converter's large load power range and high efficiency are a good fit for energy-constrained NT processors.

Power consumption in modern processor design is a key aspect. Optimizing the processor for power leads to direct savings in battery energy consumption in case of mobile devices. At the same time, many mobile applications demand high computational performance. In case of large scale computing, low power compute devices help in thermal design and in reducing the electricity bill. This paper presents a case study of a customized low power vector processor design that was synthesized on a 28 nm process technology. The processor has a programmer exposed datapath based on the transport triggered architecture programming model. The paper's focus is on the RTL and microarchitecture level power optimizations applied to the design. Using semiautomated interconnection network and register file optimization algorithm, up to 27% of power savings were achieved. Using this as a baseline and applying register file datapath gating, register file banking and enabling clock gating of individual pipeline stages in pipelined function units, up to 26% of power and energy savings could be achieved with only a 3% area overhead. On top of this, for the measured radio applications, the exposed datapath architecture helped to achieve approximately 18% power improvement in comparison to a VLIW-like architecture by utilizing optimizations unique to transport triggered architectures.

The MPEG-4 core profile enables object-based coding. A core profile encoder may also have to be able to carry out simple profile frame-based coding. Frame-based coding is, for instance, needed when the object-based functionalities are not used or the target decoder has only simple profile capabilities. cellular nonlinear networks (CNN) offer an effective method to implement the segmentation needed in object-based coding. CNN can be implemented very efficiently with dedicated parallel processor arrays. These parallel processor arrays can integrated with sensor arrays in low-power low bit-rate mobile video encoders. It is shown here that an object-based core profile encoder can have advantages in frame-based simple profile encoding. The intermediate results of a CNN segmentation algorithm can be used in computational complexity reduction of motion estimation (ME). The CNN intermediate results indicate areas of motion within a frame. The areas without motion can be then used to stop the ME or to indicate MPEG-4 skip modes. All block-based ME algorithms can benefit from this knowledge. The intermediate results of the segmentation algorithm are evaluated with the full search and MVFAST ME algorithms. Rate-distortion and computational complexity results are computed with four different reference frame schemes. Considerable improvement in output bits and computational complexity is seen without loss in subjective video quality. The method also has applications in scene change detection.

Ultra-low voltage is the key to ultra-low power consumption. Hence, there is a drive to lower the operating voltage of wireless sensor System-on-Chips as much as possible. State-of-the-art components already operate below 1V and some below 0.5V. However, commercial rechargeable lithium-ion batteries show a high nominal voltage in the range of 3.4–4.1V. Were such batteries paired with ultra-low-voltage systems, cost effective power-conversion design (without off-chip components) becomes difficult and energy will in all likelihood be lost in the conversion. While sub-2V lithium-ion batteries exist, sub-1V water-based electrolyte batteries with high energy density should also be developed. Shown here is experimental low voltage lithium battery with an ultra-low-voltage DC-DC converter / processor test system. Simulations on the DC-DC show from 12% to 74% efficiency improvement depending on the configuration. Measurements on the processor show 83% energy-delay product and 39% energy / operation improvement.

In this paper, we present a CMOS/memristor hybrid architecture for massively parallel logic computations in a CMOL-type memristive memory. The considered architecture enables bit-parallel stateful logic operations, which can be used to efficiently implement vector computations. As examples of computing schemes that benefit from the considered processing architecture, we consider the implementation of a content-addressable memory and binary cellular automata. We verify the correct operation of the considered processing architecture and algorithms using HSPICE simulations.

To minimize energy consumption of a digital circuit, logic can be operated at sub- or near-threshold voltage. Operation at this region is challenging due to device and environment variations, and resulting performance may not be adequate to all applications. This paper presents an ASIC implementation of a 32-bit RISC CPU in 28nm CMOS with wide range of adjustable voltage/frequency from 250mV/85kHz to 750mV/135MHz. The CPU employs timing-error prevention with clock stretching to enable operation with minimal safety margins while maximizing energy efficiency at a given operating point. Measurements show 3.15pJ/cyc energy consumption at 400mV, which corresponds to 39% energy savings and 83% EDP improvement compared to operation based on static signoff timing.