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1,027 results on '"Lab-STICC_UBS_CACS_MOCS"'

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1. Two upper bounds on the chromatic number

2. A hybrid grouping genetic algorithm for multiprocessor scheduling

3. VNS for high-level synthesis

4. Key research issues for reconfigurable network-on-chip

5. Using integer linear programming in test-bench generation for evaluating communication processors

6. Energy models of real time operating systems on FPGA

7. Electronic design: a new field of investigation for large scale optimization

8. Hierarchical and Multiple-Clock Domain High-Level Synthesis for Low-Power Design on FPGA

9. HLS-based Fast Design Space Exploration of ad hoc hardware accelerators: a key tool for MPSoC Synthesis on FPGA

10. Designing formal reconfiguration control using UML/MARTE

11. Modeling and Solving the Clustered Capacitated Vehicle Routing Problem

12. TAG SHEPERD: a Low Cost and Non Intrusive Man Overboard Detection System

13. Hardware Discrete Channel Emulator

14. Interactive Reference Point-Based Guided Local Search for the Bi-objective Inventory Routing Problem

15. On simulating operating environment desicions in a sane network

16. Multi-Level Reconfiguration in the DANAH Assistive System

17. Specification and os-based implementation of self-adaptive, hardware software embedded systems

18. Alert Management for Home Healthcare Based on Home Automation Analysis

19. Multicriteria Decision Making Approach For Reconfigurable Manufacturing Systems

20. A Comparative Study of Two Software Defined Radio Environments

21. Open-People: Open-Power and Energy Optimization Platform and Estimator

22. Dynamic Routing Strategy for Embedded Distributed Architectures

23. Neighborhood selection in variable neighborhood search

24. Modélisation et contrôle de la reconfiguration dynamique et partielle

25. Multi-objective Artificial Immune Algorithm for Security-constrained Multi-application NoC mapping

26. Hierarchical NoC-based security for MP-SoC dynamic protection

27. A MARTE to AADL Mapping

28. RDAL: A new language for the definition and verification of requirements against AADL and other architecture models

29. AADL Requirements Annex Explored With FAA Handbook Example

30. Maximisation du rayon de stabilité pour l'affectation d'opérations de durée incertaine sur une ligne d'assemblage

31. Interactive approach to the inventory routing problem: computational speedup through focused search

32. FPGA area time power estimation for DSP applications

33. Virtual Devices for Hot-Pluggable Processors

34. Area time power estimation for FPGA based designs at a behavioral level

35. A Modified Decomposition Algorithm for Maximum Weight Bipartite Matching and Its Experimental Evaluation

36. WHISPER: A Tool for Run-Time Detection of Side-Channel Attacks

37. Design and Multi-Abstraction-Level Evaluation of a NoC Router for Mixed-Criticality Real-Time Systems

38. Computation of 2D 8×8 DCT Based on the Loeffler Factorization Using Algebraic Integer Encoding

39. Networked Power-Gated MRAMs for Memory-Based Computing

40. A Hybrid Adaptive Strategy for Task Allocation and Scheduling for Multi-applications on NoC-based Multicore Systems with Resource Sharing

41. Back-to-Back Butterfly Network: an Adaptive Permutation Network for New Communication Standards

42. Adaptive Task Allocation and Scheduling on NoC based Multicore Platforms with Multitasking Processors

43. Multi-Context TCAM-Based Selective Computing: Design Space Exploration for a Low-Power NN

44. Industrie et pandémie, quelles mutations ?

45. Subutai: Speeding Up Legacy Parallel Applications Through Data Synchronization

46. Comparison of Market-based and DQN methods for Multi-Robot processing Task Allocation (MRpTA)

47. Memristor Overwrite Logic (MOL) for In-Memory DNN

48. Toward Secured IoT Devices: a Shuffled 8-Bit AES Hardware Implementation

49. Accélérateurs matériels sécurisés pour la cryptographie post-quantique

50. Secure Hardware Accelerators for Post Quantum Cryptography

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