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Micromagnetic simulations have been used to create reversible logic gates that utilize magnetic skyrmions as input and output signals. The geometrical design of the logic devices consists of a two-dimensional assembly of ferromagnetic nanotracks, resembling rectangular grooves. Drawing an analogy to the billiard-ball model, this study takes into account elastic collisions between magnetic skyrmions and introduces the concept of control skyrmion. The application of spin-polarized currents to the system induces the motion of magnetic skyrmions along the nanotracks. The synchronized movement of magnetic skyrmions across the operational logic gates, required for their interaction, is achieved by incorporating multiple triangular magnetic notches along the nanotracks. Short polarized current pulses are then applied through the logic gates to facilitate this process. We have successfully implemented the XOR/AND and Full Adder logic gates as well as the reversible Toffoli and Peres logic gates using skyrmion-based architectures for computing. Our results offer valuable guidelines for leveraging magnetic skyrmions as digital signals in skyrmion-based computing systems. [ABSTRACT FROM AUTHOR]

The design of a Ternary Logic Processor using CNTFETs (Carbon-Nanotube-Field-Effect-Transistor) is a challenging task, but it also has the potential to offer significant advantages over the traditional binary logic processors based on CMOS (Complementary-Metal-Oxide-Semiconductor) technology. This paper presents the design and implementation of a Ternary Logic Processor (TLP) using CNTFETs. The TLP is a single-cycle processor that operates on three-trit data. An Instruction Set Architecture (ISA) is defined, at first, for this TLP that consists of instructions of the Register type, Load-store type, Immediate type, and branch type. Based on the ISA, the architecture of the CNTFET-based TLP is proposed and the transistor level designs of the TLPs' fundamental blocks like the Ternary Instruction Fetch (TIF), Ternary Register File (TRF), Ternary Arithmetic and Logic Unit (TALU) and Ternary Data Memory (TDM) are presented. HSPICE simulations using a standard CNTFET model, are performed for the TLP and the TLPs' individual blocks and the performance parameters like the power consumption, propagation delay, and the number of CNTFETs required are calculated. In addition to this, the functionality of the processor is verified using a few of the standard programs. [ABSTRACT FROM AUTHOR]

Time-consuming ocean transportation for international trades requires enterprises to advance payments for goods, which can be fatal for small and medium enterprises with insufficient self-owned capital. Logistics finance is an effective solution for tackling this problem. However, traditional logistics finance has long been plagued by information asymmetry, tremendous paperwork, and long financing cycles. As a distributed database with characteristics of transparency, traceability, and immutability, blockchain technology shows good potential in addressing pain points on traditional logistics financing platforms. This paper focuses on the operational mechanism and value analysis of the blockchain-based port logistics finance platform. The conceptual architecture of the blockchain-based port logistics finance platform is constructed, and a value analysis model based on the Newsboy Model is established for quantitatively analysing the platform's value. The results revealed that the introduction of the blockchain into port logistics financing can significantly improve small to medium-sized enterprises' profitability by providing reliable financing channels. The results also indicate that participants' profit on the blockchain-based platform may be influenced by the speed of market expansion, initial capital size, and financing cost. This paper also discusses theoretical and managerial implications by providing insights into the participants' decision-making on the platform under different constraints. [ABSTRACT FROM AUTHOR]

This paper proposes the high speed low power analysis of 12 transistors 2x4 Low Power (LP) and Low Power Inverting (LPI) Decoders by using Dual Value Logic (DVL) and Complementary Metal Oxide Semiconductor (CMOS) Logic. A huge challenge faced by this era of developing is power reduction. The LP circuit design is a requesting issue in high performance digital frameworks, for example, microchips, DSPs and other different applications. Power and speed are the main highlights considered while comparing any design. Diminishing chip area is additionally truly impressive factor, designers need to recall when suggesting any novel design. 2x4 LP and LPI Decoders using 12T (Transistor) is used for conversion of binary inputs to associated output bits in a pattern. A novel design (CMOS logic and DVL logic) of 2x4 LP and LPI Decoders using 12T is proposed with area optimization, LP and high speed in this paper. Delay and power is evaluated between the novel design and CMOS logic. The novel design of 12T LP and LPI 2x4 Decoders is 60.72% optimized for power in contrast to CMOS logic design at a typical value of 1.8V. The proposed method has been validated using Cadence 45 GPDK (Generic Product Design Key) Virtuoso Tool. [ABSTRACT FROM AUTHOR]

With the rapid development and gradual popularization of Internet of Things technology, it is necessary to provide necessary Operation and Maintenance (O&M) services and data control for electromechanical engineering to maintain the normal function of the power system. This paper does the following research to carry out orderly and standardized management of related communication resources in power communication networks, conduct closed-loop and process-oriented management of communication O&M work, and ensure the safe, stable, and economical operation of power grids in electromechanical engineering. Firstly, the technology selection, algorithm implementation, solutions, and other related technologies that may be used in the platform design and implementation process are introduced and selected. Secondly, the research and call logic of the design and implementation of related algorithms for intelligent O&M are introduced. It includes the design and implementation of anomaly detection algorithms to monitor equipment health status and the design and construction of fault diagnosis algorithms for abnormal analysis. Finally, the simulation experiment of the proposed processing scheme is carried out on the Mininet simulation network to prove that the proposed scheme can provide a better anonymization effect when introducing low latency. The results show that the design of the gateway system realizes the module applications of the system, such as user, data storage, O&M, and fault management. Based on the technical selection, the algorithm is implemented and optimized, and the call logic of the algorithm is implemented in the O&M module. Simulation verifies that the anonymization algorithm can complete the mapping without introducing an additional delay of more than 3%. [ABSTRACT FROM AUTHOR]

The study presents a novel self‐powered ultraviolet (UV) photodetector harnessing both polarization fields and photovoltaic effects, enabling the realization of ultra‐low power, reconfigurable optoelectronic logic gates. The approach is demonstrated on a CuO/BaTiO3 heterojunction photodetector. The behavior of the photodetector is augmented by the poling effect, aligning the internal electric field of the BaTiO3 through the application of a robust external electric field, thereby facilitating the implementation of optoelectronic logic gates. In the unpoled state, the “XOR” and “OR” logic gates operated at voltages of 750 and −500 µV, respectively. However, upon poling up state, the “XOR” logic gate exhibits reduced operation voltage, operating at 500 µV, while the “OR” logic gate implements clarity at −500 µV. In the unpoled state the “AND” logic gate does not operate; however, upon poling in the downward direction, it operated at −500 µV. The achievement demonstrates successful ultra‐low‐power logic operations, utilizing voltages in the hundreds of micron scale, under a 310 nm wavelength and a light intensity of 0.52 mW·cm−2. Furthermore, controllable polarization electric fields in BaTiO3 enable the operation of “AND” logic gate in the unpoled state, presenting a promising avenue for future research in optoelectronic logic gate design. [ABSTRACT FROM AUTHOR]

Implementation of logic gates has been investigated in nonlinear dynamical systems from various perspectives over the years. Specifically, logic gates have been implemented in both single nonlinear systems and coupled nonlinear oscillators. The majority of the works in the literature have been done on the evolution of single oscillators into OR/AND or NOR/NAND logic gates. In the present study, we demonstrate the design of logic gates in bi-directionally coupled double-well Duffing oscillators by applying two logic inputs to the drive system alone along with a fixed bias. The nonlinear system, comprising both bi-directional components, exhibits varied logic behaviors within an optimal range of coupling strength. Both attractive and repulsive couplings yield similar and complementary logic behaviors in the first and second oscillators. These couplings play a major role in exhibiting fundamental and universal logic gates in simple nonlinear systems. Under a positive bias, both the first and second oscillators demonstrate OR logic gate for the attractive coupling, while exhibiting OR and NOR logic gates, respectively, for the repulsive coupling. Conversely, under a negative bias, both the first and second oscillators display AND logic gate for the attractive coupling, and AND and NAND logical outputs for the repulsive coupling. Furthermore, we confirm the robustness of the bi-directional oscillators against moderate noise in maintaining the desired logical outputs. [ABSTRACT FROM AUTHOR]

This paper critically reviews various energy-saving models used for enhancing the energy efficiency of hydrostatic power transmission drives. The system layout, component design, and controllers used are discussed in detail in its sub-category. Based on the detailed review of various energy-saving models, a novel energy-efficient hydrostatic power transmission drive of the chairlift transport system (CTS) is proposed. The rise in fluid temperature in the existing hydraulic arrangement of the CTS, owing to its continuous recirculation, is controlled by incorporating the flushing valve, while the boost pump replenishes the fluid volume loss. However, because of its loading nature, the CTS's existing power transmission drive encounters energy losses and uncontrolled fluid cooling. In the present study, the hydraulic circuit design of the existing power transmission drive of the CTS is modified to reduce energy losses. Using a variable displacement auxiliary pump in the system helps minimize the energy losses through the pressure relief valve. Also, the proposed design enhances the cooling efficiency of the flushing valve unit controlled through a suitably designed Fuzzy logic controller having a dependency on fluid temperature. The simulation model is made in MATLAB/ Simulink® environment, and the result shows that, with the increase in speed, the orifice area opening of the proportional flow control valve increases to prevent oil temperature from exceeding the operating range and the same decreases for a reduced speed. Furthermore, the proposed system exhibits a significant energy saving of 32 kJ over 300 s, demonstrating its improved efficiency compared to the existing system. [ABSTRACT FROM AUTHOR]

Platform companies use techniques of algorithmic management to control their users. Though digital marketplaces vary in their use of these techniques, few studies have asked why. This question is theoretically consequential. Economic sociology has traditionally focused on the embedded activities of market actors to explain competitive and valuation dynamics in markets. But restrictive platforms can leave little autonomy to market actors. Whether or not the analytical focus on their interactions makes sense thus depends on how restrictive the platform is, turning the question into a first order analytical concern. The paper argues that we can explain why platforms adopt more and less restrictive architectures by focusing on the design logic that informs their construction. Platforms treat markets as search algorithms that blend software computation with human interactions. If the algorithm requires actors to follow narrow scripts of behavior, the platform should become more restrictive. This depends on the need for centralized computation, the degree to which required inputs can be standardized, and the misalignment of interests between users. The paper discusses how these criteria can be mobilized to explain the architectures of four illustrative cases. [ABSTRACT FROM AUTHOR]

Magnetic skyrmions, despite being promising ultra‐low energy information carriers with wide bandwidth and nonvolatility, are not used for any universal scalable logic system. Here, a detailed understanding of skyrmion motion in nanowires under different geometries and drive conditions is established. Then, these insights are used to introduce a general Boolean‐universal gate block system with components, emulation, and simulation algorithms. The resulting system can collectively form a scalable, cascadable, and universal skyrmion logic system and produce arbitrary logic designs. The NOR, AND, OR, NAND, XNOR, and FULL ADDER gates are provided here as example demonstrations of the system. The toolkit lays the foundation for bridging the gap between theoretical exploration and practical implementation of skyrmion‐based computing. The skyrmion block components may help reduce energy consumption per logic operation after eliminating Joule heating. The insights and designs may help skyrmions be used in state‐of‐the‐art electronic design automation. [ABSTRACT FROM AUTHOR]

Parallel-connected digital valve arrays are commonly utilized in the pilot stage of the proportional directional valve to enhance dynamic performance and reliability. However, when the digital valve array is driven by a digital signal, it is difficult to optimally assign the signal pulses to each valve. If the assignment is not well executed, it can significantly reduce the switching uniformity of the digital valves or lead to performance degradation of the system. In this paper, a model-based sliding mode control strategy based on the intelligent distribution of control law is proposed and successfully applied to a proportional valve driven by digital valve arrays. The intelligent distribution strategy encompasses a logic distribution algorithm and a circular sliding distribution algorithm that automatically assigns control laws to different valves based on the rolling of the PWM signal cycle. Experimental results confirm that the proposed strategy not only simultaneously reduces the total number of valve switches and enhances the switching uniformity among the valves, but also adapts to the variation in the number of valves. The proposed strategy is not limited to the application of digital valve arrays, it is also applicable in other fields of multi-actuators driven by digital signals, and can simultaneously improve the control accuracy, lifetime, and maintenance friendliness. • A digital proportional valve is proposed, where the pilot stage consists of fixed orifices and digital valve arrays. • The intelligent distribution strategy is designed based on a logic distribution and a circular sliding distribution. • The proposed MSMC with intelligent distribution can be adapted to DVAs with any number of valves. [ABSTRACT FROM AUTHOR]

Software-Defined Networking (SDN) revolutionizes network management by decoupling control plane functionality from data plane devices, enabling the centralized control and programmability of network behavior. This paper uses the ternary system to improve the Central Processing Unit (CPU) inside the SDN controller to enhance network management. The Multiple-Valued Logic (MVL) circuit shows remarkable improvement compared to the binary circuit regarding the chip area, propagation delay, and energy consumption. Moreover, the Carbon Nanotube Field-Effect Transistor (CNTFET) shows improvement compared to other transistor technologies regarding energy efficiency and circuit speed. To the best of our knowledge, this is the first time that a ternary design has been applied inside the CPU of an SDN controller. Earlier studies focused on Ternary Content-Addressable Memory (TCAM) in SDN. This paper proposes a new 1-trit Ternary Full Adder (TFA) to decrease the propagation delay and the Power–Delay Product (PDP). The proposed design is compared to the latest 17 designs, including 15 designs that are 1-trit TFA CNTFET-based, 2-bit binary FA FinFET-based, and 2-bit binary FA CMOS-based, using the HSPICE simulator, to optimize the CPU utilization in SDN environments, thereby enhancing programmability. The results show the success of the proposed design in reducing the propagation delays by over 99% compared to the 2-bit binary FA CMOS-based design, over 78% compared to the 2-bit binary FA FinFET-based design, over 91% compared to the worst-case TFA, and over 49% compared to the best-case TFAs. [ABSTRACT FROM AUTHOR]

Despite being very old, the mining industry continues to be one of the major sources of pollution, with more people killed or injured than in all other industries. Prevention of incidents/accidents on machinery in mining pits and the issues of operator safety on mining machinery largely depend on the ergonomic adaptation of the workplace, compliance with safety procedures and policies, and organizational and other influential factors. Evidently, scarce consideration of those factors in the available literature has not given satisfactory results till now. The aim of this paper is to first set up a comprehensive model based on ergonomic factors and contextual theory, which takes into account all the influencing factors on the occurrence of incidents/accidents and represents a complex system of interdependence of influential variables of diverse, mostly stochastic nature, and then design a software solution on the given basis. In this research, based on the extensive data collected, a model was generated using the structural equations modelling methodology, which was then used to design the reasoning logic in the expert system for mitigating the risks of the operation of mining machines. An innovative solution incorporating a mathematical model of the interdependence of influential variables into the stored knowledge base offers a decision support system that provides recommendations for the maintenance of a particular mining machine, depending on the assessment of model factors in a specific decision-making situation at the higher organizational level and ergonomic suitability for the operator at the lower organizational level, and, in that manner, enables the mitigating of risky/unwanted events. [ABSTRACT FROM AUTHOR]

The interest in alternative logic technologies is continuously increasing for short nanometer designs. From this viewpoint, logic gates, full adder and D-latch designs based on graphene nanoribbon field effect transistors (GNRFETs) at 7 nm technology nodes were presented, considering that these structures are core elements for digital integrated circuits. Firstly, NOT, NOR and NAND gates were implemented using GNRFETs. Then, 28T full adder and 18T D-latch circuits based on CMOS logic were designed using GNRFETs. As the first result of this work, it was shown through HSPICE simulations that the average power consumption of the considered logic circuits employing GNRFETs was 78.6% lower than those built using classical Si-based MOSFETs. Similarly, the delay advantage of the logic circuits employing GNRFETs was calculated to be 53.2% lower than those using Si-based MOSFET counterparts. In addition, a deep learning model was developed to model both the power consumption and the propagation delay of GNRFET-based logic inverters. As the second result, it was demonstrated that the developed deep learning model could accurately represent the power consumption and delay of GNRFET-based logic circuits with the coefficient of determination (R2) values in the range of 0.86 and 0.99. [ABSTRACT FROM AUTHOR]

Edge computing enables prompt responses in IoT environments, such as the operation of autonomous vehicles and unmanned aerial vehicles. However, with the increase in sensor nodes, the computational burden on the computing node also increases. Specifically, data filtering and reduction at application nodes add to the energy burden for battery-operated devices. In this paper, we propose a preprocessing system at the application node that requires low power consumption for data transmission reduction. Based on our simulations, we identify the minimum data size needed to preserve the signal. We first design the preprocessing system using a hardware description language to evaluate its performance. Then, we implement the open-library-based MCU system, including the proposed preprocessing IP, to assess its operation and overhead. Our implementation of the preprocessing system reduces data transmission by 50% with acceptable information loss. Additionally, the area and power consumption after the logic synthesis of the preprocessing IP within the entire MCU system are evaluated at only 3.6% and 13.1%, respectively. By performing preprocessing using the MCU and proposed IP, nearly 74.4% power reduction is achieved compared to using the existing MCU core. [ABSTRACT FROM AUTHOR]

As the scale and complexity of chips continue to increase, chip design becomes increasingly challenging. Designers typically need multiple iterations to achieve satisfactory results, but the substantial time required for each modification exacerbates the time pressure in the chip design process. Incremental methods are an effective technique to shorten the development iteration time. Therefore, this paper proposes a module-based incremental layout technique utilizing the hierarchical structure of the unflattened netlist. We have developed an incremental EDA tool for mid-version evaluation, covering the process from RTL to placement DEF. This tool enables faster synthesis and layout, assisting designers in assessing the feasibility of the current RTL design, thereby accelerating the estimation of the PPA (Power, Performance, and Area) during version iterations. It aids in making better choices for RTL design and logic synthesis, consequently shortening the chip development iteration time. [ABSTRACT FROM AUTHOR]

In this work, an innovative design model aimed at enhancing the efficacy of ground-state probabilistic logic with a binary energy landscape (GSPL-BEL) is presented. This model enables the direct conversion of conventional CMOS-based logic circuits into corresponding probabilistic graphical representations based on a given truth table. Compared to the conventional approach of solving the configuration of Ising model-basic probabilistic gates through linear programming, our model directly provides configuration parameters with embedded many-body interactions. For larger-scale probabilistic logic circuits, the GSPL-BEL model can fully utilize the dimensions of many-body interactions, achieving minimal node overhead while ensuring the simplest binary energy landscape and circumventing additional logic synthesis steps. To validate its effectiveness, hardware implementations of probabilistic logic gates were conducted. Probabilistic bits were introduced as Ising cells, and cascaded conventional XNOR gates along with passive resistor networks were precisely designed to realize many-body interactions. HSPICE circuit simulation results demonstrate that the probabilistic logic circuits designed based on this model can successfully operate in free, forward, and reverse modes, exhibiting the simplest binary probability distributions. For a 2-bit × 2-bit integer factorizer involving many-body interactions, compared to the logic synthesis approach, the GSPL-BEL model significantly reduces the number of consumed nodes, the solution space (in the free-run mode), and the number of energy levels from 12, 4096, and 9–8, 256, and 2, respectively. Our findings demonstrate the significant potential of the GSPL-BEL model in optimizing the structure and performance of probabilistic logic circuits, offering a new robust tool for the design and implementation of future probabilistic computing systems. [ABSTRACT FROM AUTHOR]

With the tourism industry continuing to boom, the importance of tourism mascots in promoting and publicizing tourism destinations is becoming increasingly prominent. Three core dimensions, market trend, appearance design, and audience feedback, are numerically investigated for deeply iterating tourism mascot design. Further, a subjective and objective evaluation weighting model based on the hierarchical analysis method (AHP) and entropy weighting method is proposed, aiming to utilize the advantages of these methods and ensure the entireness and correctness of results. Taking the mascots of six famous tourist attractions in Xi'an as an example, the feasibility and effectiveness of the evaluation model are verified. Data analysis and modeling results confirm that the three core evaluation indexes of scalability, innovation, and recommendation should be focused on in the design of tourism mascots in the three dimensions of market trends, appearance design, and audience feedback. The evaluation index scores are 0.1235, 0.1170, and 0.1123, respectively, which further illustrates the priority of mascot design. The evaluation model constructed by the research provides decision-makers with a comprehensive evaluation tool from the perspective of tourist experience, and also effectively assists the optimization process of mascot design. In addition, the model has good versatility and adaptability in structural design and evaluation logic and can be widely used in the optimization and evaluation research of brand mascots. [ABSTRACT FROM AUTHOR]

This paper addresses the critical challenge of optimizing the maximum power point (MPP) tracking of photovoltaic (PV) modules under varying load and environmental conditions. A novel fuzzy logic controller design has been proposed to enhance the precision and adaptability of MPP monitoring and adjustment. The research objective is to improve the efficiency and responsiveness of PV systems by leveraging voltage and power as input parameters to generate an optimized duty cycle for a buck-boost converter. This system is tested through both simulation and experimental validation, comparing its performance against the conventional perturb and observe (P&O) method. Our methodology includes rigorous testing under diverse conditions, such as temperature fluctuations, irradiance variations, and sudden load changes. The fuzzy logic technique is implemented to adjust the reference voltage every 100 µs, ensuring continuous optimization of the PV module's operation. The results revealed that the proposed fuzzy logic controller achieves a tracking efficiency of approximately 99.43%, compared to 97.83% for the conventional P&O method, demonstrating its superior performance. For experimental validation, a 150 W prototype converter controlled by a dSPACE DS1104 integrated solution was used. Real-world testing involved both a resistive static load and a dynamic load represented by a DC shunt motor. The experimental results confirmed the robustness and reliability of the fuzzy logic controller in maintaining optimal MPP operation, significantly outperforming traditional methods. In brief, this research introduces and validates an innovative fuzzy logic control strategy for MPP tracking, contributing to the advancement of PV system efficiency. The findings highlight the effectiveness of the proposed approach in consistently optimizing PV module performance across various testing scenarios. [ABSTRACT FROM AUTHOR]

Mechanical computing has garnered significant interest as a supplement to traditional electronic computing, which often grapples with issues like high power consumption, security vulnerabilities, and susceptibility to extreme environmental conditions such as intense heat and radiation. Yet, most research in mechanical computing has been limited to the ad hoc design of simple logic gates and has not fully achieved the implementation of simple arithmetic computation within an electricity‐free framework. Additionally, progress in environmentally adaptive computing, crucial for decentralized intelligence, has also been slow. New ground is broken with the development of a mechanical transistor that synergizes a Kirigami thermomechanical sensor and a bistable actuator, enabling in‐memory computing for combinational and sequential logic. The design stands out by employing modular construction, symmetry breaking, and nonlinear materials, crafting logic gates, and memory units that respond to environmental stimuli through thermal delay. These transistors integrate design and material intelligence to establish nonvolatile memories, essential for logic‐in‐memory, and align thermal transport with mechanical deformation for environmental responsiveness. The mechanical transistor heralds a new age in mechanical computing, proving to be as versatile and vital as the electronic transistor has been in the era of modern computing. [ABSTRACT FROM AUTHOR]

The ability to predict gas emissions accurately is pivotal in managing gas control and ensuring safe mining operations. Existing internationally acknowledged gas control and prediction software does not cater to the specific conditions in Chinese coal mines. Hence, this paper introduces an object-oriented programming method to design a software tool for calculating the total gas emission quantity using the MATLAB application program designer runtime environment. The software incorporates an algorithm, data structure, framework, and module functions, all of which enable seamless integration and visualization of gas emission calculation software. This software tool mitigates the inefficiencies and inaccuracies associated with manual, different-source forecast methods. Based on the field data of the Hulonggou Coal Mine in Shanxi province, this technical software was used to predict the gas emission of the mine. The research results show that the predicted value of the technical software is close to the actual measured value. The differing estimates of the working face and coal mine output primarily account for the deviation between the tool's predicted gas emission value and the field-measured value. The underlying design logic of this technical software determines that it has good adaptability to mines with clear mining technology parameters and gas geological parameters. This study provides a valuable method for researchers and engineers seeking to improve gas emission calculation efficiency. [ABSTRACT FROM AUTHOR]

Herein, we report the synthesis of a small molecule quinoline Schiff-base "turn-on" fluorescence probe L, denoted as (2-NC9H6)C(H)=N(C6H4OCH3-p), utilizing 4-aminoanisole and quinoline-2-carboxaldehyde as precursors. The synthesized probe was comprehensively characterized through EA,1H/13C NMR, FT-IR, and ESI-MS spectral analysis. In a CH3CN/H2O solution (1/1, v/v, 0.01 M PBS buffer, pH = 7.30), probe L responded to Hg(II) with high sensitivity (LOD = 2.98 × 10−7 M) and selectivity. Upon binding to Hg(II), the fluorescence of the probe shifted from being initially off to a distinct blue emission. The probe L to Hg(II) binding ratio was 1:1 and the binding constant was 1.955 × 104 M−1. The detection mechanism of Hg(II) by probe L is due to the complex formation between the metal ion and imine nitrogen (–CH = N), thus causing chelation-enhanced fluorescence. TD-DFT studies at the B3LYP/6-31G(d) level of theory further confirmed that the complexation of L and Hg(II) occurred. Finally, probe L could reversibly identify Hg(II) upon adding EDTA, thus developing a molecular logic gate. In addition, this probe was successfully used to detect Hg(II) in actual water samples. : [ABSTRACT FROM AUTHOR]

This paper introduces a design of ternary bistale ring physical unclonable function (BRPUF) based on carbon nanotube field effect transistors (CNTFETs). PUFs can extract unique chip features from process variations and assign every chip an inherent fingerprint to be used for identification or authentication of devices. As the main point of strength for PUF security, the size of challenge-response pairs (CRPs) can be increased by adopting multi-valued logic designs. The proposed ternary BRPUF blends higher entropy into CRPs and is tested to produce unbiased response digits, thus making them more unpredictable and more resistant against machine learning attacks. The instinctive features of CNTFETs, such as intensive process variations and high tolerance against temperature fluctuations and noises, enable our design to function robustly in a wide range of operating conditions. The proposed design has been implemented using standard 32-nm CNTFET model libraries and tested by HSPICE simulations. The results elaborate the superiority of our work compared with the traditional binary BRPUFs. [ABSTRACT FROM AUTHOR]

This paper introduces a Fuzzy Logic Controller designed for an on-load tap changer within medium voltage distribution systems with bulk penetration of Distributed Energy Resources. As the on-load tap changer remains one of the most essential forms of voltage regulation in medium voltage distribution networks, improving its operation is a cost-effective response to the emerging voltage violations caused by intermittent generation during the early stages of the energy system transformation. Software-in-the-loop simulations were conducted to validate the effectiveness of the proposed algorithm compared to the conventional methods. A modified CIGRE Medium Voltage Distribution Network Benchmark in European Configuration was modelled while the controller code developed in Python 3.12 was running on a PC, both coupled in a real-time closed-loop environment. The analyses showed that the proposed algorithm managed to reduce overvoltage from 7.02% to 4.85% in the benchmark network, thus demonstrating that the algorithm is efficient and ready for on-field implementation. [ABSTRACT FROM AUTHOR]

Ground motion prediction equations (GMPEs) play a key role in seismic hazard assessment (SHA). Considering the seismo-tectonic, geophysical, and geotectonic characteristics of a target region, all the GMPEs may not be suitable in predicting the observed ground motion effectively. With a fairly large number of published GMPEs, the selection and ranking of suitable GMPEs for the design of logic trees in SHA for a particular target region have become a necessity of late. This paper presents a detailed quantitative evaluation of performance of 16 GMPEs against recorded ground motion data in two target regions, characterized by distinct seismo-tectonic, geophysical, and geotectonical nature. The dataset comprises 465 three-component spectral accelerograms corresponding to 122 earthquake events. The suitability of a GMPE is tested by two widely accepted data-driven statistical methods, namely, likelihood (LH) and log-likelihood (LLH) method. Different suites of GMPEs are shown suitable for different periods of interest. The results will be useful to scientists and engineers for microzonation and estimation of seismic design parameters for the design of earthquake-resistant structures in these regions. [ABSTRACT FROM AUTHOR]

In her book From Law and Literature to Legality and Affect, Greta Olson argues for an expansive view of the legal, which encompasses both one's Rechtsgefühl and the sociocultural normative settings one is surrounded by. Acknowledging the existence of "a variety of competing nomoi " (Olson, From Law and Literature, p.7), i.e., diverse normative environments within a given legal order, notions of law as legality, and affect as law's new Other are conceptualized as projects fostering legal pluralism. Yet, is such a pluralistic, diversified notion of legality able to challenge those normative legal-cultural conditions which still privilege cis, male, heterosexual, White, able-bodied, propertied non-immigrants? Agreeing with Roger Cotterrell that "[l]aw's interpretive communities now reflect the patterned differentiation of the social" (Law, p.100), and Olson's claim that "ideas about law are negotiated outside of the courtroom, the parliament, or even the governmental office where law and legal ordinances are directly translated into everyday life experience" (From Law and Literature, p. 20), this article examines how legality may speak back to law, in its professionalized, dogmatic sense, and to legal orders, and analyzes in which ways an understanding of law as legality may affect LGBTQIAP* rights activism. This critical queer theoretical perspective thus challenges Olson's nomoi by approaching the limitations of legal affects for trans and queer legal subjects. By analyzing the design and logic behind two recent cases of anti-trans bills in the U.S., Arkansas' HB 1570 ('Save Adolescents from Experimentation Act') and Idaho's HB 500 ('Fairness in Women's Sports Act') from a cultural studies perspective, this article examines how an expanded understanding of law as legality may affect the gendered, cis-ed, and heteronormative nature of the U.S.'s dominant legal order(s). [ABSTRACT FROM AUTHOR]

Intelligent passenger service in rail transit requires the establishment of an intelligent emergency call system. In response to the current situation of call methods, this article first analyzes the functional requirements and system requirements of the intelligent emergency call system from the perspective of passengers. Combining the system with the application of new technologies such as artificial intelligence, a call method based on both online and offline is proposed, establishing a threelevel system of intelligent calls, manual calls, and on-site calls. In addition, the use of a five-layer architecture is proposed to establish a platform for intelligent calls for assistance, which is divided into device access layer, data input layer, service logic layer, algorithm processing layer, and terminal response layer. This paper designs the response logic and service processes under this system, and uses intelligent distribution algorithms to ensure the nearby triggering and timely response to calls for assistance. Finally, from an engineering perspective, the settings of the call-for-assistance terminal equipment and the required inter-system linkage are proposed. The research in this article will provide reference for the development of intelligent emergency call systems in the future. [ABSTRACT FROM AUTHOR]

This paper introduces three new gust load alleviation control strategies, which are based on variable camber technology, to achieve the design requirements for the safety, economy, and comfort of modern civil aircraft. These strategies involve adjusting the inner and outer flap differential of wings, spoilers, and ailerons to alter the aerodynamic shape of the aircraft structure, resulting in drag reduction and gust load alleviation during stepped cruise flights. Furthermore, a logic design is provided for both the cruise drag reduction function and the gust load alleviation function. To validate the effectiveness of the proposed gust load alleviation control strategies, simulation results are presented, utilizing ride quality and wing root bending moment changes as the evaluation criteria. The presented approaches ultimately lead to the development of an optimal scheme that meets the desired design requirements. [ABSTRACT FROM AUTHOR]

Critical and logical thinkers are in high demand in the workforce. Vocational students need to possess this knowledge if they plan to work after graduation. Nevertheless, there aren't many Math Logic modules designed for students in vocational schools that have this ability. The goal of this research is to provide module that facilitating students at vocational schools to improve their critical thinking abilities. Utilizing 4-D Thiagarajan steps, this study using R&D method. Critical thinking ability tests, teacher and student answer questionnaires, and expert validation sheets are the instruments employed. Both quantitative and qualitative analysis was done on the data collected from the instruments. The data processing results demonstrate: 1) valid modules, as determined by validity test results from media, practitioners, and subject matter experts; 2) high-quality modules, as determined by student and teacher response results; and 3) useful modules, as determined by effectiveness test results in the classroom. The module can be utilized for instruction at vocational schools. [ABSTRACT FROM AUTHOR]

An N-bit priority resolver having N inputs and N outputs functions as polling hardware in an embedded system, enabling access to a resource when multiple devices initiate access requests at its inputs which may be located on-chip or off-chip. Subsystems such as data buses, comparators, fixed- and floating-point arithmetic units, interconnection network routers, etc., utilize the priority resolver function. In the literature, there are many transistor-level designs for the priority resolver based on dynamic CMOS logic, some of which are modular and others are not. This article presents a novel gate-level modular design of priority resolvers that can accommodate any number of inputs and outputs. Based on our modular design architecture, small-size priority resolvers can be conveniently combined to form medium- or large-size priority resolvers along with extra logic. The proposed modular design approach helps to reduce the coding complexity compared to the conventional direct design approach and facilitates scalability. We discuss the gate-level implementation of 4-, 8-, 16-, 32-, 64-, and 128-bit priority resolvers based on the direct and modular approaches and provide a performance comparison between these based on the design metrics. According to the modular approach, different sizes of priority resolver modules were used to implement larger-size priority resolvers. For example, a 4-bit priority resolver module was used to implement 8-, 16-, 32-, 64-, and 128-bit priority resolvers in a modular fashion. We used a 28 nm CMOS standard digital cell library and Synopsys EDA tools to synthesize the priority resolvers. The estimated design metrics show that the modular approach tends to facilitate increasing reductions in delay and power-delay product (PDP) compared to the direct approach, especially as the size of the priority resolver increases. For example, a 32-bit modular priority resolver utilizing 16-bit priority resolver modules had a 39.4% reduced delay and a 23.1% reduced PDP compared to a directly implemented 32-bit priority resolver, and a 128-bit modular priority resolver utilizing 16-bit priority resolver modules had a 71.8% reduced delay and a 61.4% reduced PDP compared to a directly implemented 128-bit priority resolver. [ABSTRACT FROM AUTHOR]

Holonomic quantum computing offers a promising paradigm for quantum computation due to its error resistance and the ability to perform universal quantum computations. Here, we propose a scheme for the rapid implementation of a holonomic swap gate in neutral atomic systems, based on the selective Rydberg pumping mechanism. By employing time-dependent soft control, we effectively mitigate the impact of off-resonant terms even at higher driving intensities compared to time-independent driving. This approach accelerates the synthesis of logic gates and passively reduces the decoherence effects. Furthermore, by introducing an additional atom and applying the appropriate driving field, our scheme can be directly extended to implement a three-qubit controlled-swap gate. This advancement makes it a valuable tool for quantum state preparation, quantum switches, and a variational quantum algorithm in neutral atom systems. [ABSTRACT FROM AUTHOR]

Supramolecular polymer networks contain non-covalent cross-links that enable access to broadly tunable mechanical properties and stimuli-responsive behaviors; the incorporation of multiple unique non-covalent cross-links within such materials further expands their mechanical responses and functionality. To date, however, the design of such materials has been accomplished through discrete combinations of distinct interaction types in series, limiting materials design logic. Here we introduce the concept of leveraging "nested" supramolecular crosslinks, wherein two distinct types of non-covalent interactions exist in parallel, to control bulk material functions. To demonstrate this concept, we use polymer-linked Pd2L4 metal–organic cage (polyMOC) gels that form hollow metal–organic cage junctions through metal–ligand coordination and can exhibit well-defined host-guest binding within their cavity. In these "nested" supramolecular network junctions, the thermodynamics of host-guest interactions within the junctions affect the metal–ligand interactions that form those junctions, ultimately translating to substantial guest-dependent changes in bulk material properties that could not be achieved in traditional supramolecular networks with multiple interactions in series. Supramolecular polymer networks have unique and useful properties due to the reversible nature of their cross-links. Here, the authors show that when two distinct supramolecular interaction classes exist within a single cross-link, new functions can result. [ABSTRACT FROM AUTHOR]

In recent times, the multi-valued logic (MVL) design has been widely explored in the designing of digital computing circuits as the goals of enhanced processing capability with reduced interconnect complexity and small chip area are achieved. Hence, this work describes the design methodology of ternary logic-based asynchronous and synchronous up-counter, down-counter, and ring-counter designs using D-flip-flops in carbon nanotube technology. Carbon nanotube-field-effect transistors (CNTFETs)' unique feature of altering the device threshold voltage by making variations in CNT diameter is exploited for the realization of multiple voltages in ternary logic design. Here the principle of the master-slave scheme is adopted for the designing of Dual shift-single shift and Single shift-dual shift-D-flip-flop circuits using the cyclic property of shifting operators. These flip-flop designs are further extended to construct multiple-digit counter structures which are suitable for realizing the logic functionality of up-counter, down-counter, and ring-counter designs. To exploit ternary logic increased computation capability benefit, a mode control up/down counter circuit is designed in which a single module is generating up and down-counting sequence based on applied mode input. To investigate the performance of the proposed designs, the simulations are performed using the Synopsys HSPICE simulator considering the 32 nm Stanford CNTFET model. According to the simulation results, a maximum energy consumption reduction up to 55% is obtained compared to the counterpart. Hence, the increased computational capability of three-valued logic is exploited in the presented work to achieve energy enhancements in designing ternary sequential circuits. [ABSTRACT FROM AUTHOR]

The presence of turning points (stationary points like maxima and minima) in the Parameter-versus-state map (PSM) curve of a memristor can be beneficial in several memristive uses like multi-level logic design, multi-bit memories, and chaos generation circuits. Surprisingly the memristors with these types of PSM curves exhibit multiple crossing points in the transient input v-i contours. In this paper, the memductance model has been derived for such non-linear memristors exhibiting multi-cross-over characteristics. In the presented framework, the coefficients-related condition for the multi-turning point PSM curve has been derived, a necessary condition for the multi-crossing v-i contour. The condition related to the memristor operating parameters has also been reported taking both input signal and initial states into consideration. To realise the derived memductance model corresponding to the three cross-over memristive behaviour, an OTA-based memristor emulator has been developed. Unlike some existing fractional order non-symmetric multi-crossing memristor emulators, the proposed emulator circuit realises an integer order memristor function operating at moderate frequencies. The realised emulator uses only four OTAs and three grounded passive circuit elements with no external multiplier. For the CMOS implementation of employed OTA, the simulation results are obtained to verify the three pinch-off behaviour. [ABSTRACT FROM AUTHOR]

Industrial control systems (ICS) require system design and operation under cyber-attacks. This study aims to design a fallback control system that can switch from normal control to fallback control and verify its superiority. The target system is a factory automation (FA) system consisting of a normal programmable logic controller (PLC) and a fallback PLC. In this system, we design a fallback logic that takes over control in the case of cyber-attacks. The design of this logic requires a system model that manages smooth state transitions between normal control and fallback control in an integrated manner under cyber-attacks. In response, we model a control program in the framework of discrete event systems (DESs) and apply supervisory control to derive a supervisor model that can manage the system in an integrated manner. To ensure the controllability of the FA system during cyber-attacks, we design a control specification that includes a detection function to enable rapid switching of the control state. As a result, we generate the fallback logic from the supervisor model with guaranteed controllability under cyber-attacks and implement it in a fallback PLC to verify the effectiveness of the proposed logic. [ABSTRACT FROM AUTHOR]

Purpose: This study aims to increase the novelty of clothing design and fabric texture. The element library that can be used for design is systematically summarized. The element database can also be continuously filled according to the existing logic to realize the diversity of design. Improve the theory of fashion design, expand the designer's design ideas and improve design efficiency. Clear design steps and logic can help students and machines learn the design process and promote the development of intelligent design. And verify the feasibility of the simulation software to assist pleated clothing design. Design/methodology/approach: Firstly, according to the logical framework of origami theory, different innovative designs and combined designs are made for the basic units of hyperbolic paraboloid, and the element library that can be used for design is systematically summarized. This database can also be continuously filled according to the existing logic to realize the diversity of design. Secondly, it summarizes three methods of pleated element filling clothing – uniform filling method, the irregular filling method and geometric addition method – that improve the theory of fashion design, expand the designer's design ideas and improve design efficiency. Clear design steps and logic can help students and machines learn the design process and promote the development of intelligent design. Finally, the virtual software is used to simulate the effect of pleated clothing, and the three-dimensional simulation software 3dclo is used to make an empirical study on the application of hyperbolic paraboloid origami in clothing pleated design to verify the feasibility of the simulation software to assist pleated clothing design. Findings: The theoretical results of hyperbolic paraboloid origami are collected and arranged to establish the element library of hyperbolic paraboloid origami. The results expand the designer's design ideas and auxiliary design technology and improve the design efficiency using a sample of hyperbolic paraboloid fabric to verify its practicability and three-dimensional clothing simulation software for exploring the design. The design rules of hyperbolic paraboloid clothing and the realization method of fabric are summarized, including the expansion and combing of elements, the application of size and shape and the method of combination. Research limitations/implications: Owing to the hyperbolic paraboloid origami's length shrinkage, the loose computation of clothing requires targeted computation. This paper solely applies a paper model for estimating the shrinkage, and then we tend to subsequently explore the way to precisely compute the porosity, to determine the existing differences in the two-dimensional shrinkage of hyperbolic paraboloid creases of varying materials and to know if the clothing after large-scale production is capable of reaching the anticipated value. Practical implications: The exploration of this experiment brings a new 3D experiment process to the design process. Social implications: This experiment brings new possibilities for the development of virtual fitting and virtual display in the industry. Originality/value: This study combines hyperbolic paraboloid origami and clothing and combs and expands the unit with logical thinking to expand the designer's design ideas. [ABSTRACT FROM AUTHOR]

Monotonic circuits are a class of input–output mode (IOM) asynchronous circuits that are relaxed compared to quasi-delay-insensitive (QDI) IOM asynchronous circuits in terms of signaling the completion of internal processing. Some recent works have demonstrated the superiority of monotonic logic over QDI logic for arithmetic circuits such as adders and multipliers. This paper presents a new monotonic asynchronous two-bit full adder (TFA) that can be duplicated and cascaded to form a ripple-carry adder (RCA). While an RCA is a slow adder with respect to synchronous design, with respect to IOM asynchronous design an RCA is a noteworthy adder since it has perhaps the least reverse latency that is not attainable through other IOM asynchronous adders. Conventionally, an RCA is constructed via a cascade of one-bit full adders (OFAs). An OFA adds two input bits along with any carry input and produces a sum bit and any carry output. On the other hand, a TFA simultaneously adds two pairs of input bits along with any carry input and produces two sum bits and any carry output. Using our proposed monotonic TFA, we realized an RCA to compare its performance with RCAs constructed using different asynchronous OFAs, and RCAs constructed using existing TFAs. We considered the popular delay-insensitive dual-rail scheme for encoding the adder inputs and outputs, and two 4-phase handshake protocols, namely return-to-zero handshaking (R0H) and return-to-one handshaking (R1H) for communication separately. We used a 28 nm CMOS process for implementation and considered a 32-bit addition as an example. Based on the design metrics estimated, the following inferences were derived: (i) compared to the RCA using the state-of-the-art monotonic OFA, the RCA incorporating the proposed TFA achieved a 26% reduction in cycle time for R0H and a 28.5% reduction in cycle time for R1H while dissipating almost the same power; the cycle time governs the data application rate in an IOM asynchronous circuit, and (ii) compared to the RCA comprising an early output QDI TFA, the RCA incorporating the proposed TFA achieved a 22.3% reduction in cycle time for R0H and a 25.4% reduction in cycle time for R1H while dissipating moderately less power. Also, compared to the existing early output QDI TFA, the proposed TFA occupies 40.9% less area for R0H and 42% less area for R1H. [ABSTRACT FROM AUTHOR]

In simulation-based training, learners apply skills in an environment that approximates the real conditions of work. Trainers who design a simulation also employ assumptions about the design of communication, or how they believe learners should communicate. More specifically, simulation-based training events draw work groups' attention to communication expectations related to timing, timelines, and timeliness. Competing perspectives may produce temporality tensions. To better understand how temporality tensions affect work and workers, I conducted a qualitative case study of a large, multi-agency disaster-response exercise (the 'Tall Grass' exercise), which simulated a search-and-rescue operation. I identified competing design logics related to synching work streams, pacing activities, and providing feedback or input at the 'right' time, and I identified counterproductive effects of adopted communication designs. In response to the findings, I suggest alternative designs for communication that offer better function, fit, and attention to fragmented interests. [ABSTRACT FROM AUTHOR]

This article presents a comparative simulation-based control logic design process. It uses the Control Description Language (CDL) and the ASHRAE Guideline 36 high-performing building control sequences with the Modelica Buildings Library (MBL) to demonstrate a comparative analysis of two control designs for a data center chilled water plant. Details include a description of the closed-loop plant and control design methodology, including sizing and parameterization, base and alternative (Guideline 36) control logic with software implementation structure, and outline of the simulation experimentation process. The selected control designs are paired with comparable chilled water plant configurations. The models include a chiller, a water-side economizer, and an evaporative cooling tower. The plant provides cooling at 27ºC zone supply air temperature to a data center in Sacramento, CA. The comparative simulation results examined the impacts of a selected control logic detail, and present an example model-based design application. Overall, the simulation results showed a 25% annual and a 18% summer energy use reduction for alternative controls. This shows that simulation-based control logic design performance evaluation can improve energy efficiency and resilience aspects of system controls at large. [ABSTRACT FROM AUTHOR]

Achieving complete magnetization switching is a significant challenge in the electrical control of magnetic devices. In this paper, we propose a structure called bicomponent multiferroic nanomagnet (BMN) to study strain-mediated magnetization switching behavior. The BMN consists of a complete piezoelectric layer and a magnetostrictive layer made of bicomponent magnetic materials. Our team successfully developed a dynamic model for the magnetization of BMNs. By micromagnetic simulation, the results show that the strict requirements for a precise applied voltage period can be overcome in such a BMN, and a 180° magnetization switching can be achieved with only a square-wave voltage signal and a pulse width (tth) larger than 0.5 ns, given that the amplitude of the voltage is 60 mV. In addition, we also investigated the tolerance window of material composition and geometry, and proved that BMNs have sufficient error margins and the switching rate of BMNs can reach 1.67 GHz within the error margins at room temperature. Our proposed BMN device has a simple structure and low energy consumption as it does not require precise piezoelectric layer design or stringent voltage clocking requirements. The energy consumption per switching is only 7.3 aJ. These findings provide significant guidance for the design of nanomagnetic logic and memory devices and lay a strong foundation for the application of strain-mediated magnetization switching technology. [ABSTRACT FROM AUTHOR]

This investigation reports all optical parity generators and checkers based on quantum dot semiconductor optical amplifiers at 200 Gb/s. The proposed circuit has been realized by using SOA-MZI configuration with a quantum dot as an active region in SOA. A parity generator consists of three inputs and utilizes 2 XOR logic while a parity checker employs 3 XOR logic with 4 inputs. Cross-phase modulation in SOA has been exploited in the design of XOR logic. MZI configuration converts phase modulation to amplitude modulation to achieve desired boolean equation of XOR. A wide and clear eye diagram has been obtained for the parity generator and checker outputs. The quality factor for the parity generator and checker outputs obtained are 17.2 and 15.1 respectively also the extinction ratio for both outputs are more than 15 dB. [ABSTRACT FROM AUTHOR]

Quantum dot Cellular Automata (QCA) may be viewed as the poten- tial digital logic design alternative to supplant the current CMOS Technol- ogy. The logical design is based on the polarization of electrons to transfer information which results in a huge improved performance metric in terms of speed, power & area. This paper demonstrates a Reversible Arithmetic Processor (RAP) architecture design with Reversible Multiplexer (RM) and Reversible Functional Gate in QCA. The QCA Designer-E simulation tool has been used to design and verify all the proposed archi- tecture and the energy dissipation has been simulated using a coherent vector energy engine setup. The total and average energy dissipation per cycle of our proposed RAP using QCA are 3.91 × 10−1 eV and 3.56 × 10−2 eV respectively. Moreover, the power dissipation of proposed RAP is 1.3 nW. Regarding cell count, area, latency, and energy dissipation, the proposed architecture beats out the existing architecture. [ABSTRACT FROM AUTHOR]

In this study, a wearable exoskeleton arm was designed and controlled with different control methods to help people with muscle disorders in their arms and support treatment. The developed robot arm was transferred to Simulink software with the Simmechanics application. Two electromyography (EMG) muscle sensors and the ADXL335 position and acceleration sensors attach to the human arm's biceps and triceps muscle areas. As the human moved the arm, data were obtained from the EMG muscle sensors and the ADXL335 position and acceleration sensor. The received data were first trained with the fuzzy logic algorithm. The same data were then trained with machine learning algorithms in Simulink software. It has been determined that the best result is the quadratic support vector machine (SVM) algorithm. The fuzzy logic algorithm trained with the PID controller block and the received sensor data have been added to the degrees of freedom regions that will enable rotation in the block diagram of the previously exported system. Later, the fuzzy logic block was removed and the machine learning algorithm, the quadratic SVM algorithm, was added. The designed system was operated with two different control systems, and the control algorithm closest to the human arm movement was determined. In addition, each part of the system, whose design was prepared, was removed and assembled separately with a 3D printer. ESP32 microcontroller development board was used to control the system, and it was run in real-time with EMG muscle sensors and position sensors. [ABSTRACT FROM AUTHOR]

Memorizing nanodrives are distinguished by a large variety of majority trigger structures, which are the basic fragments of the the nanocircuit of a high integration level. The paper describes the synthesis of reliable sequential nanodevices of single- electronics based on the technology of quantum cellular automata. When constructing majority nano-circuits with memory, the theory of finite automata is used. The order of computer design of different types of arithmetic and logic nanodevices is analyzed. High-speed parallel-acting and paraphase control nanoregisters control are created. [ABSTRACT FROM AUTHOR]

Today, various applications in different domains increasingly rely on high-performance computing (HPC) to accomplish computations swiftly. Integrating one or more programming models alongside the used programming language enhances system parallelism, thereby improving its performance. However, this integration can introduce runtime errors such as race conditions, deadlocks, or livelocks. Some of these errors may go undetected using conventional testing techniques, necessitating the exploration of additional methods for enhanced reliability. Formal methods, such as temporal logic, can be useful for detecting runtime errors since they have been widely used in real-time systems. Additionally, many software systems must adhere to temporal properties to ensure correct functionality. Temporal logics indeed serve as a formal frame that takes into account the temporal aspect when describing changes in elements or states over time. This paper proposes a temporal-logic-based testing tool utilizing instrumentation techniques designed for a dual-level programming model, namely, Message Passing Interface (MPI) and Open Multi-Processing (OpenMP), integrated with the C++ programming language. After a comprehensive study of temporal logic types, we found and proved that linear temporal logic is well suited as the foundation for our tool. Notably, while the tool is currently in development, our approach is poised to effectively address the highlighted examples of runtime errors by the proposed solution. This paper thoroughly explores various types and operators of temporal logic to inform the design of the testing tool based on temporal properties, aiming for a robust and reliable system. [ABSTRACT FROM AUTHOR]

Many IoT applications require high computational performance and flexibility, and FPGA is a promising candidate. However, increased computation power results in higher energy dissipation, and energy efficiency is one of the key concerns for IoT applications. In this paper, we explore adiabatic logic for designing an energy efficient configurable logic block (CLB) and compare it to the CMOS counterpart. The simulation results show that the proposed adiabatic-logic-based look-up table (LUT) has significant energy savings for the frequency range of 1 MHz to 40 MHz, and the least energy savings is at 40 MHz, which is 92.94% energy reduction compared to its CMOS counterpart. Further, the three proposed adiabatic-logic-based memory cells are 14T, 16T, and 12T designs with at least 88.2%, 84.2%, and 87.2% energy savings. Also, we evaluated the performance of the proposed CLBs using an adiabatic-logic-based LUT (AL-LUT) interfacing with adiabatic-logic-based memory cells. The proposed design shows significant energy reduction compared to a CMOS LUT interface with SRAM cells for different frequencies; the energy savings are at least 91.6% for AL-LUT 14T, 89.7% for AL-LUT 16T, and 91.3% AL-LUT 12T. [ABSTRACT FROM AUTHOR]

Building biological computers is one of the most intensively pursued goals of modern synthetic biology. The new TriLoS tristate-based logic synthesis platform, published in this issue of Cell , offers a long-awaited solution to scale up the complexity of biocomputing, opening a path to move this field beyond proof-of-principle demonstrations. [ABSTRACT FROM AUTHOR]