Search

This paper presents a study of six physical transmission line transformers (TLTs) designed to provide wideband output matching for laterally diffused metal oxide semiconductor (LDMOS) transistors within a push-pull amplifier operating in the 1.8-30 MHz spectrum with an output power of 600W. While the mathematical model of TLTs is well described in the literature, the impact of physical construction methods on impedance matching and real amplifier performance is more challenging to ascertain. This paper compares six different TLTs built on various ferrite cores and employing different implementations of transmission lines. Return loss below -14 dB was achieved from 1.65 to 37.4 MHz, with most of the tested transformers exhibiting return loss better than -10 dB up to 50 MHz. The study also presents the impact of transmission line implementation on impedance matching using both special-purpose low impedance coaxial cable and a combination of general-purpose coaxial cables connected in parallel. Comparison of three chosen transformers in a real RF amplifier shows that using parallel transmission lines can lead to a return loss comparable to that of a specialpurpose coaxial cable, although at the cost of lower efficiency and output power. Second harmonic cancellation effect was also investigated for three transformers. [ABSTRACT FROM AUTHOR]

To enhance the electrical safe operation area (eSOA) of laterally diffused metal oxide semiconductor (LDMOS) transistors, a novel reduced surface electric field (Resurf) structure in the n-drift region is proposed, which was fabricated by ion implantation at the surface of the LDMOS drift region and by drift region dimension optimization. Technology computer-aided design (TCAD) simulations show that the optimal value of Resurf ion implantation dose 1 × 1012 cm−2 can reduce the surface electric field in the n-drift region effectively, thereby improving the ON-state breakdown voltage of the device (BVon). In addition, the extended n-drift region length of the Ld design also improves device BVon significantly, and is aimed at reducing the current density and the electric field, and eventually suppressing the n-drift region impact ionization. The results show that the novel 60 V nLDMOS has a competitive BVon performance of 106.9 V, which is about 20% higher than that of the conventional one. Meanwhile, the OFF-state breakdown voltage of the device (BVoff) of 88.4 V and the specific ON-resistance (RON,sp) of 129.7 mΩ⋅mm2 exhibit only a slight sacrifice. [ABSTRACT FROM AUTHOR]

This article presents a method for estimating the power consumption of radio frequency (RF) power amplifiers (PAs) within the 5G new radio (NR) downlink (from the base station to user equipment), particularly in the absence of user data. We also outline an RF PA design strategy for low power consumption and high efficiency. When no user data signal is transmitted, in the 5G NR downlink, considerably fewer fixed-transmission signals, such as reference signals, are involved compared to 4G long-term evolution (LTE). This results in a reduced operating time for the PA and decreased power consumption. The PA power consumption was calculated by analyzing the signal and nonsignaling periods in a 5G NR downlink without user data. Furthermore, the power consumption is estimated based on measurements obtained from the continuous wave (CW) or the full-buffer signal input/output of a fabricated PA. The fabricated PA is a Doherty amplifier, whose impedance conversion circuit consists of a transmission line connected in parallel to two T-shaped stubs. It can short-circuit the second to the fifth harmonics at the same connection point. The fabricated Doherty amplifier achieved a drain efficiency of 60.2% at a saturated output power of 48.6 dBm at 1852.5 MHz. At a 6 dB back-off from saturation, its drain efficiency was 51.9%. In addition, at a 39.6 dBm modulated signal output, the spurious levels up to the fifth harmonic were −15.8 dBm/MHz or less.

Modern System-on-Chip (SoC) architectures necessitate low-voltage (LV) core transistors featuring excellent digital, analog, and radio frequency (RF) properties, as well as thick oxide transistors serving as robust I/O buffers and high-voltage (HV) transistors essential for efficient power management. This study presents a comprehensive DC to RF characterization, a detailed modeling strategy, and subsequent model parameter extraction for commercially produced LV and HV Fin Field Effect Transistors (FinFETs) at 14/16 nm technology. The industry-standard BSIM-CMG compact model is modified to accurately capture the characteristics of the HV FinFET devices integrated with the digital LV FinFETs for SoC applications. A detailed analysis of the DC, analog, and RF performance of LV, I/O, and HV FinFETs compared to the contemporary planar CMOS technology is performed. The large-signal performance of the device is evaluated using the developed model and validated with the measured data. Finally, a concise overview of the performance indicators associated with the modeled device is also presented.

To enhance the electrical safe operation area (eSOA) of laterally diffused metal oxide semiconductor (LDMOS) transistors, a novel reduced surface electric field (Resurf) structure in the n-drift region is proposed, which was fabricated by ion implantation at the surface of the LDMOS drift region and by drift region dimension optimization. Technology computer-aided design (TCAD) simulations show that the optimal value of Resurf ion implantation dose 1 × 1012 cm−2 can reduce the surface electric field in the n-drift region effectively, thereby improving the ON-state breakdown voltage of the device (BVon). In addition, the extended n-drift region length of the Ld design also improves device BVon significantly, and is aimed at reducing the current density and the electric field, and eventually suppressing the n-drift region impact ionization. The results show that the novel 60 V nLDMOS has a competitive BVon performance of 106.9 V, which is about 20% higher than that of the conventional one. Meanwhile, the OFF-state breakdown voltage of the device (BVoff) of 88.4 V and the specific ON-resistance (RON,sp) of 129.7 mΩ⋅mm2 exhibit only a slight sacrifice.

We propose a pioneering approach that integrates optimization algorithms and technology computer-aided design to automatically optimize laterally-diffused metal-oxide-semiconductors (LDMOS) with a field-oxide structure. We define the ratio of the square of the breakdown voltage divided by the specific on-resistance as the figure-of-merit (FOM) and the objective function of our optimization. We compare the performance of three different algorithms: Nelder-Mead, Powell, and Bayesian Optimization. We show how the LDMOS performance evolves as each of the three optimization algorithms reach their optimized structure. We show that a straightforward Nelder-Mead optimization leads to a local optimum when optimizing over six input parameters. We find that Bayesian Optimization is the most data-efficient method to find the global optimized structure in the multi-domain design space.

In this paper, a 4H-SiC lateral gate MOSFET incorporating a trench MOS channel diode at the source side is explored to improve the reverse recovery characteristics. In addition, a 2D numerical simulator (ATLAS) is used to investigate the electrical characteristics of the devices. The investigational results have demonstrated that the peak reverse recovery current is reduced by 63.5%, the reverse recovery charge is reduced by 24.5%, and the reverse recovery energy loss is decreased by 25.8%, with extra complexity in the fabrication process. [ABSTRACT FROM AUTHOR]

We propose a lateral double-diffused metal oxide semiconductor (LDMOS) structure in which several N-type windows with higher densities than its drift region are located deep in the drift region. We have named the proposed LDMOS as several N-type windows LDMOS (SNW-LDMOS). This work has two main ideas: the first is to reduce the specific on-resistance due to the presence of the windows with a doping density higher than the drift region. The second is the increase in breakdown voltage due to the creation of new peaks by the N-type windows located in the drift region, where these windows can optimize the distribution of the electric field. On the other hand, these windows modify the electric field by expanding the depletion region in the drift region. Therefore, the breakdown voltage of the proposed SNW-LDMOS transistor increases. Also, the results from a two-dimensional numerical simulation show that, by optimizing the N-windows, the figure of merit and the current flow are significantly improved compared to a conventional LDMOS device. [ABSTRACT FROM AUTHOR]

This article presents a detailed characterization and analysis of a 45 V LDMOS device from production technology across a wide temperature range from 33 to 385 K. For the first time, quasi-saturation behavior is consistently observed throughout the entire temperature range studied. Compared to prior published data, this device shows some notable differences, including a substantially higher saturation temperature of around 200 K for threshold voltage and subthreshold swing due to band tail and a typical low on-resistance down to 33 K, free of freezeout. To account for the observed temperature dependencies, we propose improved semi-empirical temperature scaling equations for the PSPHV model. We extend its applicable temperature range down to 33 K from the previous lower limit of 240 K. The enhancement models the temperature behaviors of key device parameters, including threshold voltage, subthreshold swing, mobility, velocity saturation, drift resistance, and quasi-saturation effects. These results provide new insights into the low-temperature behavior of LDMOS devices for cryogenic electronics applications. • We show cryogenic data of high voltage SOI LDMOS from production technology down to 33 K. • We observe a high saturation temperature of around 200 K for the threshold voltage and subthreshold swing. • We verify that the PSPHV model can be extended down to the cryogenic range with modifications. • We develop semi-empirical temperature scaling equations valid from 385 K to 33 K. [ABSTRACT FROM AUTHOR]

Abstract In this study, design considerations of a new device structure are presented to improve the self‐heating effect (SHE) and the breakdown voltage of the Deep Gate LDMOS (Lateral Double Diffused Metal Oxide Semiconductor) transistor and compared with a conventional LDMOS (C‐LDMOS). In this case, triple oxide trenches with an N+ trench are embedded in the drift region. These trenches create additional peaks in the electric field profile, so the electric field is modified. The authors demonstrate that by optimising the trenches, the breakdown voltage of the device increases. Also, a partially buried oxide is used in the proposed structure to create a conduction path that significantly reduces the SHE. Moreover, the results indicate that the specific on‐resistance, lattice temperature, and breakdown voltage of the proposed device are improved considerably compared to the C‐LDMOS.

In this paper, to achieve a high figure of merit (FOM), a new Lateral Double Diffused Metal Oxide Semiconductor (LDMOS) device is presented. This new proposed LDMOS consists of the double p-window located in the buried silicon dioxide's depth, leading to an extra peak in the electric field curve. By optimizing the double p-window, the breakdown voltage of the proposed structure is increased by modifying the electric field profile. We call the proposed device a double p-window in buried silicon dioxide of LDMOS (DPWSD-LDMOS). Also, to reduce the self-heating effect (SHE), we have used partial silicon on insulator (PSOI) technology in the proposed DPWSD-LDMOS structure. Also, the effects of the proposed LDMOS device, including the electric field, the potential, the impact of the double p-window in the FOM, and the lattice temperature are analyzed. By two-dimensional ATLAS simulator, a conventional LDMOS (C-LDMOS), a conventional PSOI LDMOS (CPSOI-LDMOS), and the proposed DPWSD-LDMOS devices are simulated and compared. The results show that the FOM of the proposed structure improves by about 226% and 67% compared with the C-LDMOS and the CPSOI-LDMOS devices, respectively. [ABSTRACT FROM AUTHOR]

This work demonstrated a potential LDMOS structure based on trench-gate on SOI known as dual-channel trench LDMOS (DCTLDMOS). DCTLDMOS structure is designed by incorporating trenches in the conventional LDMOS to improve the cut-off frequency (ft), drain current (ID), transconductance (gm), maximum oscillation frequency (fmax), and breakdown voltage (Vbr) with reduced cell pitch length. The modified structure is suitable for medium (50–90 V) power amplifier circuits. In the proposed device the gate electrodes is placed vertically in oxide filled trenches made in drift layer of unit cell and drain/source contacts are placed horizontally on the top of the device. The significance of trench gate structure is to reduce the field lines in the drift layer and consequently improves the device performance parameters. The proposed structure reduces the specific on-resistance (Ron,sp) and enhances the ID, increasing the peak gain (gm) resulting higher fmax and ft. Further, other two SiO2 filled trenches are placed on both sides of p-base to enhance reduced-surface-field (RESURF) effect. This effect increases the breakdown voltage (Vbr). Based on 2-D software (ATLAS) results, the DCTLDMOS provides 2.5 times increase in ID, 25% reduction in Ron,sp, 84% higher gm, 50% improvement in Vbr, 58% increase in ft, and 20% increase in fmax over the planer LDMOS. [ABSTRACT FROM AUTHOR]

An ultra-low specific on-resistance 4H-SiC power laterally diffused metal oxide semiconductor (LDMOS) device is proposed for 1200V-class applications. In the proposed SiC LDMOS device, a double-trench gate is introduced to reduce the channel region resistance. And a p-type variation lateral doping (VLD) region is also employed in the drift region, which not only optimizes the surface electric field and improves the breakdown voltage, but also increases the doping concentration of the N-drift region, resulting in a low drift region resistance. So that, the proposed device achieves an ultra-low specific on-resistance ( ${R} _{\mathrm{ on,sp}}$ ). Numerical Simulation results show that the ${R} _{\mathrm{ on,sp}}$ of the proposed SiC LDMOS is 3.5 $\text{m}\boldsymbol{\Omega }\cdot {\mathrm{ cm}}^{2}$ with a breakdown voltage of ~1460V, which is reduced by more than 46% compared with the conventional field-plate SiC LDMOS with a ${R} _{\mathrm{ on,sp}}$ of 6.6 $\text{m}\boldsymbol{\Omega }\cdot {\mathrm{ cm}}^{2}$ and a breakdown voltage of ~1210V. The transconductance of the proposed device is improved greatly. And the trade-off relationship between the ${R} _{\mathrm{ on,sp}}$ and the breakdown voltage is also significantly improved compared with those of the conventional device and the previous literature.

We analytically and numerically investigate the performance of Laterally-Diffused Metal-Oxide-Semiconductor (LDMOS) transistors with Semi-circular Field OXide (S-FOX) focusing on mid-voltage (30 V – 100 V) power applications. We derive an analytical relation between breakdown voltage and on-resistance to realize the ideal behavior of the drift region for an LDMOS with S-FOX. Then, we find the optimized drift doping concentration minimizing the on-resistance at a given breakdown voltage. We introduce a new figure-of-merit for the drift region of a lateral device with S-FOX. We finally verify our ideal analytical findings with numerical results modeled and simulated in a commercial Technology Computer-Aided Design (TCAD).

In this paper, a new lateral double-diffused metal oxide semiconductor (LDMOS) device is presented by considering the SiC window under the drift region and in the buried oxide. The SiC region with a higher band gap than silicon is useful for increasing the breakdown voltage. However, the mismatch of the SiC and silicon limits the application of this material. In the new SiC window in the LDMOS (SCW-LDMOS) structure, a Si3N4 layer is considered between the silicon of the drift region, as well as interface charges at the interface of the SiC/SiO2. Simulation with the two-dimensional ATLAS simulator shows that the SCW-LDMOS transistor has higher breakdown voltage than the conventional LDMOS structure (C-LDMOS). Moreover, the SiC window creates new peaks in the horizontal electric field and thus reduces the main peaks, which is the main reason for achieving high breakdown voltage. To achieve excellent performance of the new proposed transistor, accurate values of the SiC length, thickness, and doping density are determined. Also, the proper thickness of the Si3N4 is chosen in this study. [ABSTRACT FROM AUTHOR]

We present a new silicon on insulator (SOI) laterally diffused metal oxide semiconductor (SOI-LDMOS) transistor for high power operations. Our main idea is to amend the electric field between the gate and drain area. By reducing the electric field, the created holes due to impact ionization will be amended, and the number of generated holes in the channel significantly reduces. In this work, we modify the shape of the drift region. The form of the drift area alters from the rectangular shape to the M-shape. Therefore, the M-shape drift region is extended into the buried oxide (BOX), and so we called the proposed structure as M-shape drift SOI-LDMOS (MSD-SOI-LDMOS). Due to embedding a triple N-type silicon layer into the BOX layer, we achieve two goals. First, at the higher electric field, these layers absorb the created holes due to impact ionization. Second, the impact of self-heating reduces because of silicon's higher thermal conductivity than the BOX layer. Results have shown that the proposed structure performs better with a higher breakdown voltage of about 116 V and a low specific on-resistance of about 31.2 mΩ/cm−2. [ABSTRACT FROM AUTHOR]

In this article, a novel high- k and equivalent variable lateral doping 4H-SiC lateral double-diffused metal oxide semiconductor (LDMOS) field-effect transistor with improved performance is proposed and calibrated by numerical simulation. The three-dimensional equivalently P-top region is employed in the drift region, and only one additional ion implantation step is needed to achieve variable lateral doping (VLD) technique. The VLD technique combined with the high- k dielectric in the drift region, not only increases the doping concentration of N-drift region, but also optimizes the electric field distribution in the drift region. Simulation results indicates that the BV , specific on-resistance and the short-circuit withstand time of the proposed H k VLD LDMOS are improved by 48.91%, 53.6% and 60.2% respectively, compared with those of the conventional LDMOS device. • The VLD technique combined with the high- k dielectric in the drift region, not only increases the doping concentration of the N-drift region, but also optimizes the electric field distribution in the drift region. • The left side of the P-top region is connected to the source, which suppresses the channel length modulation effect of the proposed LDMOS, thereby diminishing the saturation current and enhancing the short-circuit capacity of the device. • Simulation results indicate that the BV , specific on-resistance and the short-circuit withstand time of the proposed H k VLD LDMOS are improved by 48.91%, 53.6% and 60.2% respectively, compared with those of the conventional LDMOS device. [ABSTRACT FROM AUTHOR]

The motivation of this paper increases the bandwidth of power amplifier to multioctave by matching circuit, which consists of ferrite balun, 4:1 transformers and RC network feedback to make atrade-off between gain and VSWR. So this work discusses the design of a push-pull power amplifier demonstrating over more than a decade bandwidth using matching networks to achieve [30–800] MHz bandwidth. Matching transformer techniques can be used in order to minimise the return loss and increase the gain. Modification of the classical topology, based on inductive compensation of the parasitic capacitance of ferrite, has been proposed and used to design a 1:4 transformer. Practically, miss-match and heating is the main concern for broadband performance of high power amplifier. Coaxial cable and ferrite are also used to dissipate the heat (high temperature) resulting from the amplification power, in addition to installing the board on a cooler with appropriate dimensions, so we get the best match and stability. The simulation results are compared with the measurements. The measured results show that 20.5–17.46 dB of gain, 50.5–47.46 dBm of output power, and 50.9 of drain efficiency are delivered. [ABSTRACT FROM AUTHOR]

In this paper, a novel high voltage superjunction lateral double diffused MOSFETs (SJ-LDMOS) using a variable high permittivity (VHK) dielectric trench is presented. A relatively high HK dielectric is in the upper trench, which is connected with the drain electrode to suppress the high electric field (E-field) peak under the drain by the dielectric reduced surface field (RESURF) effect. In addition, a relatively low HK dielectric is at the bottom of the trench. On the one hand, the substrate is effectively depleted by a suitable HK dielectric layer, and the vertical depletion region of the substrate is greatly expanded. On the other hand, the overall vertical bulk E-field distribution is modulated by the E-field peaks generated at the position of varying K dielectric. A more uniform bulk E-field distribution is obtained for VHK SJ-LDMOS, leading to a high breakdown voltage (BV). Compared to the conventional SJ-LDMOS, the blocking voltage per micron of the drift region of VHK SJ-LDMOS has increased by 41.2%. Besides, compared with the SJ-LDMOS with a uniform-K, the BV of VHK SJ-LDMOS is improved by about 9.5%. The condition of the optimal range of the variable high permittivity is also presented. Meanwhile, the proposed VHK SJ-LDMOS has good conduction characteristics and heat dissipation [ABSTRACT FROM AUTHOR]

In this study, design considerations of a new device structure are presented to improve the self‐heating effect (SHE) and the breakdown voltage of the Deep Gate LDMOS (Lateral Double Diffused Metal Oxide Semiconductor) transistor and compared with a conventional LDMOS (C‐LDMOS). In this case, triple oxide trenches with an N+ trench are embedded in the drift region. These trenches create additional peaks in the electric field profile, so the electric field is modified. The authors demonstrate that by optimising the trenches, the breakdown voltage of the device increases. Also, a partially buried oxide is used in the proposed structure to create a conduction path that significantly reduces the SHE. Moreover, the results indicate that the specific on‐resistance, lattice temperature, and breakdown voltage of the proposed device are improved considerably compared to the C‐LDMOS. [ABSTRACT FROM AUTHOR]

This paper investigates the double dielectrics enhancement LDMOS (DDE LDMOS) with high-k field dielectric and low-k buried dielectric. The analytical models of the potential and electric field, optimal breakdown voltage and drift doping concentration are established for this novel LDMOS. The validity of the analytical models is confirmed by the simulation results. Based on the analytical and simulated results, the modulation mechanism of the high-k field dielectric and low-k buried dielectric on the electric field and breakdown characteristics of DDE LDMOS are analyzed and compared. Compared to the conventional LDMOS, the specific on-resistance of DDE LDMOS is reduced by 19%, the breakdown voltage and figure of merit (FOM) of the DDE LDMOS can be improved by 62% and 222.4% when the permittivity of high-k field dielectric and low-k buried dielectric are 100 and 2. Meanwhile, the transfer characteristic, output characteristic, frequency characteristic, and switching characteristic of the DDE LDMOS are also discussed.

In this work, four kinds of lateral double-diffused MOS (LDMOS) devices with different split shallow trench isolation (STI) structures (Device A: LDMOS with traditional split-STI, Device B: LDMOS with slope-STI, Device C with step-STI and Device D with H-shape-STI) have been fabricated and the hot-carrier reliabilities also have been investigated due to the serious environment they are endured. The maximum bulk current (Ibmax) stress and the maximum gate voltage (Vgmax) stress have been carried out and the inner mechanism of device degradation have been investigated successfully. With the assistance of the T-CAD simulation tools, it is found that the main damage point locates at the STI conners with a mount of interface states generation, inducing serious degradation for these four devices. The Device D owns high hot-carrier reliability due to its special structure with narrow split-STI. The worst device is Device C because of the presence of extra STI damage point. Finally, a mechanism verification, the charge pumping (CP) method has been applied to better understand this work.

In this paper, we have proposed a simple and zero-cost technique to improve ON-state and reliability performance of LDMOS transistors. We introduced doping gradient in the channel by optimizing position of the P-Well mask during test structure design/layout. Through proper device design, fabrication and measurement on different test structures, we have shown that the graded channel significantly improves the drive capability (upto ~30%), analog FoMs and hot-carrier reliability of LDMOS transistors without any penalty on the OFF-state performance. The performance improvement is independent of drift region design (breakdown voltage). The device physics behind different observations is also discussed with detailed TCAD simulations.

An ultralow specific on-resistance ( ${R} _{\mathrm{ on,sp}}$ ) accumulation-mode LDMOS (ALDMOS) is proposed and investigated by simulations and experiments. The proposed ALDMOS features two separated integrated diodes (SID) above the N-drift surface, which forms high density electron accumulation layer in the on-state. Meanwhile, the SID not only assists depleting the N-drift to increase the N-drift doping centration ( ${N} _{\mathrm{ d}}$ ) in the off-state, but also modulates the lateral electric field to improve the breakdown voltage (BV). Thus, the proposed SID ALDMOS could achieve ultralow ${R} _{\mathrm{ on,sp}}$ and maintain high BV simultaneously. The layout and key fabrication processes of the SID ALDMOS are demonstrated. The measured results show that the SID ALDMOS realizes a BV of 483V and ${R} _{\mathrm{ on,sp}}$ of 29.3m $\boldsymbol{\Omega } $ .cm2, with a high FOM value of 7.96MW/cm2. Its ${R} _{\mathrm{ on,sp}}$ is decreased by 33.7% compared with triple RESURF LDMOS at the same BV.

The present work proposes a novel dual dummy gate Silicon-on-Insulator Laterally Double Diffused Metal-Oxide-Semiconductor (SOI-LDMOS) transistor. TCAD simulation shows considerable promise to enhance the dc, analog/RF, and switching performance than the single dummy gate and conventional SOI-LDMOS transistor. A strong accumulation region (SAR) forms under the optimum biased dummy gates (at the semiconductor surface in the drift region) that assist in increasing the On-current and, thereby, reducing the On-Resistance. The proposed device exhibits ~93.5% improvement in On-current (ION), ~144% increase in transconductance (gm), ~29% reduction in specific On-resistance (RON,sp), ~360% improvement of intrinsic gain compared to the conventional SOI-LDMOS transistor. The dummy gates, which are in short with the source contact at zero potential, act as a field plate, and minimize the gate to drain capacitance due to the shielding effect. Improvement in the cut-off frequency (fT) and the maximum frequency (fMAX) is reported. The proposed device also offers a decrease of the gate to drain charge (QGD) leading to reduction in Figure of Merit RON,sp × QGD by ~31%. The increase of maximum power per unit area by ~52% is reported for power amplifier applications. It is shown that improving the On-State performance by tuning the dummy gate bias gives a simple, new, and cost-effective technology solution for power electronics applications. [ABSTRACT FROM AUTHOR]

In this paper, a 4H-SiC lateral gate MOSFET incorporating a trench MOS channel diode at the source side is explored to improve the reverse recovery characteristics. In addition, a 2D numerical simulator (ATLAS) is used to investigate the electrical characteristics of the devices. The investigational results have demonstrated that the peak reverse recovery current is reduced by 63.5%, the reverse recovery charge is reduced by 24.5%, and the reverse recovery energy loss is decreased by 25.8%, with extra complexity in the fabrication process.

In this article, we investigate by TCAD simulation, the combination triple reduced surface field (triple‐RESURF) and trenched‐gate to design an n‐type laterally diffused metal‐oxide‐semiconductor (LDMOS) transistor with high performance. While similar structures reported in the literature, on the one hand, use either the triple‐RESURF or trenched‐gate at once, on the other hand, those features require at least one additional mask each. We have been able to achieve both features in one transistor with only eight masks at the front‐end of line (FEOL), and one less annealing. Therefore, our proposition will be cheaper and provide better performance. The structure is obtained by re‐organizing the process steps, re‐using other existing masks, and exploiting positive and negative photoresist photolithography. The resulting specific on‐state resistance (RON,SP) is 94 mΩmm2, and the breakdown voltage (BV) is 71 V. But, most importantly a high transconductance (gm) at high gate voltages, with acceptable off‐state leakage current (Ioff), which translates into better RF performance overall than what is reported in the literature. The maximum oscillation frequency (fMAX) and cut‐off frequency (fT) could reach up to 76 and 43 GHz, respectively. Our device targets fully integrated IoT ASICs that require power amplifiers. [ABSTRACT FROM AUTHOR]

The analytical model and mechanism of homogenization field (HOF) for lateral power devices is developed in this article. The HOF structure features periodical voltage sustaining cells connected in series from source to drain, which introduces the periodic field modulation to realize the 3-D homogenization of electric field. In the model, the periodic electric field distribution of the HOF structure is obtained by solving the Poisson’s equation in one half HOF-cell. Then, a design formula is deduced by considering the optimal field distribution. Two lateral double-diffused metal–oxide semiconductor (LDMOS) devices using the HOF structure were fabricated to demonstrate the analytical model. The analytical model is in good agreement with both the simulations and experiments. In the experiments, a low $R_{ \mathrm{\scriptscriptstyle ON},sp}$ of 53.3 $\text{m}\Omega \cdot $ cm2 was realized under a high ${V}_{B}$ of 669.5 V, achieving a HOF LDMOS with high figure of merit FOM $= {V}_{B}^{2}/{R}_{ \mathrm{\scriptscriptstyle ON},sp}$ of 8.41 MW/cm2. [ABSTRACT FROM AUTHOR]

This paper details a robust parameter extraction flow for the PSPHV LDMOS transistor model. The procedure uses a global scaling parameter set and accounts for self-heating. We describe how to determine parameters associated with important physical effects specific to PSPHV: non-uniform lateral channel doping; the Kirk effect; internal drain voltage clamping; and the drain expansion effect. The method is verified on devices from different technologies. Verilog-A code for PSPHV is publicly available.

To elaborate on the relationship between sophisticated 2-D doping profile of drift region and device's breakdown behavior, a unified analytical model for the SOI LDMOS is developed in this paper. The Effective Substrate Voltage (ESV) concept is proposed so that the derivation of electric field and breakdown voltage can be simplified significantly. The ESV indicates that the influence of 2-D doping in the drift region can be equivalent to a virtual substrate potential. By using the proposed model, the role of 2-D drift doping, both continuous or discrete doping profile, in SOI LDMOSs' off-state breakdown behavior is investigated along with the TCAD simulations and experimental results. The good agreement between the analytical, measured and simulated results validates the accuracy of the developed model. A unified RESURF criterion is derived to idealize the electric field in the drift region and therefore maximize the breakdown voltage by optimizing the lateral and vertical drift doping profiles and geometric parameters. The proposed approach provides a universally applicable tool to explore the breakdown mechanism of SOI LDMOS with various drift doping profiles.

This paper deals with the breakdown voltage studies on a new lateral diffusion p‐channel MOSFET(LDMOS) and development of an optimal structure based on the breakdown voltage and on‐state resistance. In this new structure, the channel region (n‐body) and the lightly doped drain (LDD) structure were formed by a self‐aligned process. This approach leads to the saving of one mask level during fabrication. Two‐dimensional simulation was carried out on various parameters such as the horizontal and vertical electric field intensities, the impact generation profiles, generation recombination, impact generation before and after breakdown, the carrier concentration, electron and hole current densities and the conduction current densities of the structure to ascertain the behaviour of breakdown voltage and the on‐state resistance. Breakdown voltages closer to −162 V have been obtained in these structures. [ABSTRACT FROM AUTHOR]

This paper presents a fully integrated three-way Doherty architecture to address the challenges of 5G applications using laterally-diffused metal-oxide semiconductor (LDMOS) technology. By using the so-called CDS cancelation method for the Doherty combiner design, a wideband impedance transformation is achieved, that combined with the three-way Doherty power amplifier (DPA) architecture allows for high efficiency in deep back-off, with a reduced load modulation for high bandwidth. Throughout this paper, the design approach and realization are described, while multiple critical design challenges will be addressed such as low frequency drain resonance optimization, impact of in-package coupling effects, and linearity versus efficiency tradeoff. Two state-of-the-art three-way fully integrated LDMOS DPA monolithic microwave integrated circuit (MMICs) are presented to demonstrate how these measures have been successfully applied to different power amplifier (PA) line-up components for 5G base station systems. First, a 60 W 1.8–2.2 GHz multi-stage device for driver application in true dual-band operation is presented. The circuit design pays special attention to extended PA video bandwidth thanks to integrated passive device. After digital pre-distortion (DPD) in dual-band operation, this highly linear device achieves an outstanding adjacent channel leakage ratio (ACLR) of −56 dBc for a 2cLTE 20 MHz 8 dB peak-to-average ratio signal spaced by 345 MHz, thus 385 MHz instantaneous bandwidth (IBW), with 29% efficiency at 35 dBm, 12 dB output back-off (OBO). Second, the simulation and measurement results of a 55 W 2.6 GHz multi-stage DPA for massive-MIMO final stage application are presented, which yields an excellent linearized efficiency of 49% using a 200 MHz 10cLTE signal with an ACLR lower than −47.5 dBc. For 8cLTE 20 MHz (160 MHz IBW), the device yields 50% efficiency with −50.7 dBc ACLR linearized after DPD. The achieved efficiency is well comparable to published GaN DPAs. These results were achieved by improved simulation techniques to minimize frequency dispersion and thus allow high efficiency operation over wide bandwidth. Both devices show that LDMOS is not only a mature technology which allows those PAs to be reliable and low-cost for mass production in very compact packages, but also provide best-in-class RF performance according to the needs of 5G base station systems. [ABSTRACT FROM AUTHOR]

A 1200V 4H-SiC lateral double-diffused MOSFET (LDMOS) featuring a lightly doped P-top layer at the source side, and a high-doped N-well layer arranged between the channel and P-top layer is proposed. In order to promote the simulation accuracy, Sentaurus Process Tool that can simulate the oxidation, ion implantation, annealing, diffusion, etc. is used for structure establishment in this letter. In the ON-state, the electric potential at the end of the channel can be modulated and lowered due to the existence of P-top layer. The P-top layer can shield the voltage from the drain side, which results in the reduced saturation current ($\text{I}_{\text {dsat}}$), especially at high drain-source voltage ($\text{V}_{\text {DS}}$). The introduction of the N-well layer ensures that the P-top layer has almost no impact on the linear current ($\text{I}_{\text {dlin}}$). Compared with the conventional SiC LDMOS, the $\text{I}_{\text {dsat}}$ at $\text{V}_{\text {DS}}\,\,=400\text{V}$ of the proposed LDMOS decreases by 24.2% with no degradation in the $\text{I}_{\text {dlin}}$ and the OFF-state breakdown voltage (BV). Benefiting from the suppressed $\text{I}_{\text {dsat}}$ , the proposed SiC LDMOS achieves a ON-state BV 366V higher than that of the conventional SiC LDMOS at the gate-source voltage of 20V. Since the short-circuit capability of the SiC power devices is much sensitive to the $\text{I}_{\text {dsat}}$ , the 24.2% reduction in $\text{I}_{\text {dsat}}$ can predict a considerable enhanced short-circuit capability. Simulation results show that the short-circuit withstand time can be improved by 105%. [ABSTRACT FROM AUTHOR]

A novel ultralow on-resistance strained silicon-on-insulator (SOI) lateral double-diffused MOSFET with silicon-germanium (Si1-xGex) P-top layer and trench gate (PSiGe-TG LDMOS) is proposed in this letter. The Si1-xGex P-top layer (PSiGe) as a stressor introduces the beneficial stress in the drift and channel regions to enhance the electron mobility. Besides, in the off state, both P-top layer and trench gate (TG) jointly assist in depleting the N-drift region, which leads to an allowable highly-doped N-drift region. As a consequence, PSiGe-TG LDMOS realizes an ultralow specific on-resistance (${R}_{\text {on,sp}}$) resulting from the highly-doped N-drift region. Furthermore, the enhanced electric field in the trench oxide leads to an increase in breakdown voltage (BV). The simulation results show that, compared with the trench-gate SOI LDMOS (TG LDMOS) and the trench-gate SOI LDMOS with Si-based P-top layer (PSi-TG LDMOS), the introduction of PSiGe layer leads to 42% and 26% reduction in ${R}_{\text {on,sp}}$ , respectively. The figure-of-merit (FOM) of PSiGe-TG LDMOS increases from 8.1 MW/cm2 of TG LDMOS and 9.4 MW/cm2 of PSi-TG LDMOS to 12 MW/cm2, which realizes a superior performance. [ABSTRACT FROM AUTHOR]

In this paper, a novel high voltage superjunction lateral double diffused MOSFETs (SJ-LDMOS) using a variable high permittivity (VHK) dielectric trench is presented. A relatively high HK dielectric is in the upper trench, which is connected with the drain electrode to suppress the high electric field (E-field) peak under the drain by the dielectric reduced surface field (RESURF) effect. In addition, a relatively low HK dielectric is at the bottom of the trench. On the one hand, the substrate is effectively depleted by a suitable HK dielectric layer, and the vertical depletion region of the substrate is greatly expanded. On the other hand, the overall vertical bulk E-field distribution is modulated by the E-field peaks generated at the position of varying K dielectric. A more uniform bulk E-field distribution is obtained for VHK SJ-LDMOS, leading to a high breakdown voltage (BV). Compared to the conventional SJ-LDMOS, the blocking voltage per micron of the drift region of VHK SJ-LDMOS has increased by 41.2%. Besides, compared with the SJ-LDMOS with a uniform-K, the BV of VHK SJ-LDMOS is improved by about 9.5%. The condition of the optimal range of the variable high permittivity is also presented. Meanwhile, the proposed VHK SJ-LDMOS has good conduction characteristics and heat dissipation

This letter presents the optimization of the output combining network for a high‐power broadband Doherty power amplifier (DPA), based on the adoption of X‐parameters. The technique relies on the large‐signal vector network characterization of the prospective 3‐port DPA subcircuit. The characterization stage was carried out implementing the devices termination by the multisection artificial transmission line technique, thus allowing to terminate the devices with more accurate impedance value across the frequency band. This was validated by the development of the output combiner of a DPA prototype based on a pair of silicon laterally diffused MOSFETs (Si‐LDMOS). It was optimized in the band from 640 to 920 MHz, while the experimental characterization has been compared with a previous similar design. The DPA prototype exhibited a peak power of 54.4 dBm at centre frequency, with a peak drain efficiency (DE) up to 62% and 56% respectively at peak power and at 8‐dB input power back‐off. The data show a significant improvement with respect to the previous implementation of the same device technology and input network. This is due to the accuracy of the X‐parameter model based simulations, which is estimated to be 5.6 E‐3 in terms of normalized mean error. [ABSTRACT FROM AUTHOR]

Double silicon drift layers are used to reduce the specific on-resistance (Ron,sp) for a trench-gate-integrated lateral double-diffused MOSFET (DDL TG LDMOS) based on SOI technology in this paper. A trench-gate is incorporated into the oxide trench, a n-type drift layer with a high doping concentration is introduced on the topside of the original drift layer around the oxide trench, and a p-type pillar layer with a high doping concentration is inserted between the dual drift layers. First, the incorporated trench-gate constitutes dual current conduction channels, which decreases the Ron,sp. Second, the whole electric fields on the device surface and around the oxide trench are modulated on the basis of RESURF condition, leading to a higher breakdown voltage (BV) at off-state. Finally, the doping concentration of the drift layers is increased by an assistant depletion effect from the p-pillar, which not only improves the BV but also reduces the Ron,sp. Consequently, compared with those of the conventional trench SOI LDMOS on the same drift region of 18 μm and top silicon layer of 25 μm, a higher BV of 477 V and a lower Ron,sp of 32.1 mΩ∙cm2 are obtained for the DDL TG SOI LDMOS, while BV is improved by 33.5% and Ron,sp is reduced by 92.9%, respectively.

To reduce specific on-resistance (Ron,sp) of power devices, a novel SOI (silicon-on-insulator) trench gate LDMOS with heavily doping L-shaped P/N pillars and vertical dual-trench-gates is proposed in this paper, and its physical mechanism and electrical performance are investigated by numerical simulation. The L-shaped P-pillar raises the optimal doping impurity concentration of the drift region (Nd) remarkably from 1.7 × 1015 cm−3 to 1.25 × 1016 cm−3 by causing assistant depletion effect for drift region, hence a lower specific on-resistance (Ron,sp) with a 3.6 mΩ·cm2 is achieved. Meanwhile, the voltage capacity of the new structure is improved resulting from two new electric-field peaks produced by L-shaped P/N pillars. Consequently, a much lower Ron,sp and a higher breakdown voltage (BV) are achieved by the proposed structure. Simulated results show that the Ron,sp, BV, and Baliga’s figure of merit (FOM, FOM = BV2/Ron,sp) for the new structure are improved by 84.3%, 31.4%, and 991%, respectively, in comparison with the conventional trench LDMOS.

A Lateral Double-diffused Metal Oxide Semiconductor (LDMOS) with side triangular field plate (STFP) is proposed for improving the breakdown voltage (BV) and reducing the specific on-resistance (Ron,sp). The main feature of the novel LDMOS is the STFPs at both ends of the drift region, and they are fabricated into the dielectric pillars. With the introduction of the STFPs, the electric field peaks at the P-well/N-drift and N+/N-drift junctions are reduced effectively. The STFPs together with the dielectric pillars modulate the surface and vertical electric field distributions, which enhances the BV. Meanwhile, the doping concentration of the silicon pillars in the drift region is optimized and thus reduces the Ron,sp. The simulation results indicate that the BV of 379 V and the Ron,sp of 37.3 mΩ·cm2 are achieved by the STFP-LDMOS. The figure of merits (FOM) of the STFP-LDMOS is 2.7 times compared with the conventional LDMOS without STFPs. The STFP-LDMOS demonstrates a great trade-off between the Ron,sp and BV.

A novel Homogenization Field Technology (HOFT) in lateral power devices is proposed and experimentally proved in this letter. By introducing the periodically discrete metal insulator semiconductor (MIS) structure, which realizes periodic equal potential and self-charge balance, the HOFT obtains almost uniform surface and bulk electric field distributions in the voltage sustaining layer. Therefore, the new device harvests both higher breakdown voltage VB and lower specific on-resistance Ron,sp than those of the conventional reduced surface field (RESURF) technology in much higher and wider doping dose range. The experiment of the HOFT device realized a VB of 672 V and a Ron,sp of 56.7 $\text{m}\Omega ~\cdot $ cm2 under a high doping dose of $5.6\times 10^{{12}}$ cm−2, which represents a reduction of 33.8% when compared with the theoretical value of the triple RESURF technology. [ABSTRACT FROM AUTHOR]

In power devices, the resistance of the drift region is the main factor for determining the performance. To reduce the on-resistance, a novel lateral double-diffused MOSFET with variable resistivity of the drift region (VR LDMOS) is proposed in this letter. In the off state, the low doping concentration in the drift region is used to obtain high resistivity to support the reverse voltage. In the on state, the resistivity is significantly reduced by introducing electrons. This is different from the constant resistivity in the drift region of the conventional LDMOS. Ultralow on-resistance is obtained by the variable resistivity of the drift region. The simulation results show that the on-resistance is greatly reduced from 28.9m $\Omega \cdot $ cm2 of the conventional LDMOS to 1.5 $\text{m}\Omega \cdot $ cm2 of the VR LDMOS, which is almost 95% lower with the same 228 V breakdown voltage. Moreover, the current density is also been improved, which is 5 times higher than that of the conventional LDMOS. [ABSTRACT FROM AUTHOR]

A super-junction (SJ) deep-trench (DT) lateral double-diffused metal-oxide-semiconductor transistor improved by tilting the DT sidewalls is proposed. The incline of sidewalls introduces some vertically varying charges into the SJ drift regions on both sides of the DT. Therefore, the adverse effect of the DT on the surface electric field distribution is withstood, and the device can approach an ideal state of charge-balance. Simulation results show compared with a conventional device, which has the same drift region concentration and the same size but the perpendicular sidewalls, the proposed device presents a better figure of merit over 2.5 times higher. Besides, a feasible fabrication process for the proposal is presented and discussed.