Search

Spiking neural networks (SNNs) have been getting more research attention in recent years as the way they process information is suitable for building neuromorphic systems effectively. However, realizing SNNs on hardware is computationally expensive. To improve their efficiency for hardware implementation, a field-programmable gate array (FPGA) based SNN accelerator architecture is proposed and implemented using approximate arithmetic units. To identify the minimal required bit-width for approximate computation without any performance loss, a variable precision method is utilized to represent weights of the SNN. Unlike the conventional reduced precision method applied to all weights uniformly, the proposed variable precision method allows different bit-widths to represent weights and provide the feasibility of maximizing truncation effort for each weight. Four SNNs adopting different network configurations and training datasets are established to compare the performance of proposed accelerator architecture using the variable precision method with the proposed one using the conventional reduced precision method. Based on the experimental results, more than 40% of the weights require less bit-width when applying the variable precision method instead of the reduced precision method. With the variable precision method, the proposed architecture achieves 28% fewer ALUTs and 29% less power consumption than the proposed one using the reduced precision method.

Ranging from circuit-level characterization to designing a platform architecture, developing a design automation tool, and fabricating a System on Chip (SoC), this article deals with the entire development process for ultralow-power (ULP) SoCs for Internet-of-Things (IoT) end nodes. More precisely, this article first focuses on the unique characteristics of the ULP circuits, the temperature effect inversion (TEI), i.e., the delay of the ULP circuits decreases with increasing temperature. Existing TEI-aware low-power (TEI-LP) techniques have incredible potential to further reduce the power consumption of conventional ULP SoCs, but there is a critical limitation to be widely adopted in real SoCs. To address this limitation and realize the ULP SoCs that can fully benefit from the TEI-LP techniques, this article proposes a new TEI-inspired SoC platform (TIP) architecture. On top of that, taking into account that the highly complex, time consuming, and labor-intensive development process of these ULP SoCs may hinder their widespread use for IoT end nodes, this article presents a new electronic design automation tool to accelerate ULP SoC development, RISC-V express (RVX). Finally, by using the RVX, this article introduces a TIP prototyping chip fabricated in 28-nm FD-SOI technology. This chip demonstrates that power savings of up to 35% can be achieved by lowering the supply voltage from 0.54 to 0.48 V at 25 °C and 0.44 V at 80 °C while continuing to operate at a target 50-MHz clock frequency.

This article presents a highly secure and convenient biometric system for user recognition based on body channel characteristics for electric signal transmission. In the proposed framework, the user can provide reliable biometric features of body channel responses (BCRs) simply by touching an electrode surface on the device with a finger. To realize and verify the proposed approach, we acquired the BCR data from 15 subjects for approximately six weeks through experiments conducted in a customized measurement setup suited to the principle of signal transmission in the human body channel. The proposed BCR-based biometric feature (BBF) comprises a series of envelope vectors of the received BCR when applying up- and down-chirp signals to the human body, which is extracted by an interpolative method based on peak detection. The BBFs are effectively separable according to the subjects because the features magnify quantitative differences in the aspect of path losses and power delay profiles of individual BCRs for the frequency range between 1 and MHz. The classification performance was evaluated by splitting the dataset into ${80\%}$ and 20% for the training and testing, respectively, using conventional machine learning algorithms with uncorrelated 40 session datasets for the respective subjects. The highest average classification accuracy was achieved by the kernel-based support vector machine approximately 95.8% without observable and biased misidentification cases among the subjects. In addition, the analysis of receiver operating characteristic curves shows that the proposed classifiers are robust to decision boundaries at various threshold settings.

Human body communications (HBCs), employing the human body as a signal transmission medium, can provide efficient and intuitive methods to form a network in the body. This article presents a comprehensive study for a highly reliable HBC system, including body channel modeling, transceiver design, and performance evaluation through implementation, in consideration of practical sensor network environments for wearable and implantable devices applicable to healthcare and biosignal acquisition. Body channel characteristics based on capacitive couplings, such as root mean square delay spread and mean path gain (MPG), were explored by measuring the body impulse responses under 12 experimental conditions, determined by the variation in body postures and device locations between the wrist and positions assumed under the scalp through a customized experimental setup with micropig-derived biomembranes (MBMs) used for wrapping the devices to emulate an implantable environment. The proposed transceiver design for digital transmission, including a preamble structure and signal modulation method supporting a maximum data rate of 1 Mb/s, was verified through the performance evaluations conducted for examining the frame detection probability and bit error rate (BER) in the body channel model at multiple operating frequencies of 32, 42, and 64 MHz. The proposed system reliability was demonstrated by the achievement of a BER of below ${4.7\,\times \, }{10}^{-8}$ through battery-powered implemented devices with dimensions of ${30\times 30 }\,\,{\text {mm}}^{2}$ , comprising a digital signal processing module (DSPM) for signal generation and detection processes, and an analog front-end module (AFEM) for recovering the received signal from signal deterioration by severe path loss and time-dispersive effect in the body channel.

Human body communications (HBCs) have recently emerged as an innovative alternative to the current radio frequency communications for realizing wireless body area networks (WBANs) using the human body as a transmission channel without wired or wireless connections. This article addresses the provision of reliable modeling of the human body as a passage of the electric signal delivery based on the impulse response measurement through the proposal of a measurement setup and signal processing techniques applicable to wearable devices for healthcare and biosignal acquisition. In the experiments, customized impulse signals were applied to the body using battery-powered devices isolated to the earth ground for the operating environments of wearable devices. The impulse responses passed through the body were measured by considering 52 measurement conditions determined by the device locations from the head to ankle and the body postures. Body channel transfer functions (BCTFs) for the respective conditions were derived by an adaptive filter approach using an iterative algorithm to minimize the mean squared error between the measured and modeled impulse responses. The channel analysis parameters, such as mean path loss, root-mean-square delay spread, and mean and maximum excess delays, were analyzed based on the measured body impulse responses. In addition, the practical bit-error-rate performance for HBC based on the BCTFs reproducing intersymbol interference effects caused by the delay spreads of the body channels was explored to verify communication reliability in terms of the transmitter structures adopting digital transmission, sorts of human body channels, data rates, and operating frequencies.

In this study, reduced precision operations are investigated in order to improve the speed and energy efficiency of SNN implementation. Instead of using the 32-bit single-precision floating-point format, small floating-point format and fixed-point format are used to represent SNN parameters and to perform SNN operations. The analyses are performed on the training and inference of a leaky integrate-and-fire model-based SNN that is trained and used to classify the handwritten digits in MNIST database. The analysis results show that for SNN inference, the floating-point format with 4-bit exponent and 3-bit mantissa or the fixed-point format with 6-bit integer and 7-bit fraction can be used without any accuracy degradation. For training, a floating-point format with 5-bit exponent and 3-bit mantissa or a fixed-point format with 6-bit integer and 10-bit fraction can be used to obtain full accuracy. The proposed reduced precision formats can be used in SNN hardware accelerator design and the selection between floating-point and fixed-point can be determined by design requirements. A case study of SNN implementation on field-programmable gate array device is performed. With reduced precision numerical formats, memory footprint, computing speed, and resource utilisation are improved. As a result, the energy efficiency of SNN implementation is also improved.

A 17.8–34.8 GHz (64.6%) locking range current-reuse injection-locked frequency multiplier (CR-ILFM) with dual injection technique is presented in this paper. A dual injection technique is applied to generate differential signal and increase the power of the second-order harmonic component. The CR core is proposed to reduce the power consumption and compatibility with NMOS and PMOS injectors. The inductor-capacitor (LC) tank of the proposed CR-ILFM is designed with a fourth-order resonator using a transformer with distributed inductor to extend the locking range. The self-oscillated frequency of the proposed CR-ILFM is 23.82 GHz. The output frequency locking range is 17.8–34.8 GHz (64.6%) at a 0-dBm injection power without any additional control including supply voltage, varactor, and capacitor bank. The power consumption of the proposed CR-ILFM is 7.48 mW from a 1-V supply voltage and the die size is 0.75 mm × 0.45 mm. The CR-ILFM is implemented in a 65-nm CMOS technology.

An 18.8–33.9 GHz, 2.26 mW current-reuse (CR) injection-locked frequency divider (ILFD) for radar sensor applications is presented in this paper. A fourth-order resonator is designed using a transformer with a distributed inductor for wideband operating of the ILFD. The CR core is employed to reduce the power consumption compared to conventional cross-coupled pair ILFDs. The targeted input center frequency is 24 GHz for radar application. The self-oscillated frequency of the proposed CR-ILFD is 14.08 GHz. The input frequency locking range is from 18.8 to 33.8 GHz (57%) at an injection power of 0 dBm without a capacitor bank or varactors. The proposed CR-ILFD consumes 2.26 mW of power from a 1 V supply voltage. The entire die size is 0.75 mm × 0.45 mm. This CR-ILFD is implemented in a 65 nm complementary metal-oxide semiconductor (CMOS) technology.

In this paper, multi-mode signal generator using fractional-N phase locked loop (PLL) and multi-mode generator (MMG) for K-band Doppler, frequency modulated continuous wave (FMCW) and frequency shifting key (FSK) radar sensor application is proposed. This signal generator is proposed to fulfill efficient multi-mode operation without additional circuit and component. The proposed signal generator uses MMG to modulate output frequency of voltage-controlled oscillator (VCO) by changing the division value of fractional-N PLL. This structure using MMG is designed to operate in master or slave mode and it can vary not only modulation pattern but also the bandwidth and pulse repetition interval (PRI) according to the input code. This work is realized using a 1P9M 60nm CMOS process and power consumption is 25 mW from 1-V supply voltage. The phase noise is −85 dBc/Hz at 1-MHz offset at the frequency of 24 GHz.

This paper proposes a new structure of 24-GHz class-C voltage-controlled oscillator (VCO) using an auto-adaptive bias technique. The VCO in this paper uses a digitally controlled circuit to eliminate the possibility of start-up failure that a class-C structure can have and has low phase noise and a wide frequency range. To expand the frequency tuning range, a 3-bit cap-bank is used and a triple-coupled transformer is used as the core inductor. The proposed class-C VCO implements a 65-nm RF CMOS process. It has a phase noise performance of &minus, 105 dBc/Hz or less at 1-MHz offset frequency and the output frequency range is from 22.8 GHz to 27.3 GHz, which consumes 8.3&ndash, 10.6 mW of power. The figure-of-merit with tuning range (FoMT) of this design reached 191.1 dBc/Hz.

Human body communications (HBCs) realize wireless body area networks (WBANs) using the human body as a transmission channel without wired or wireless connections. While presenting various approaches for measurement and analysis of the human body channel, previous studies require additional interpretations of their results to obtain practical design parameters for a desired communication system. This paper addresses the provision of specific design guidelines based on the proposed channel measurement for capacitive coupling HBC employing digital transmission, adopted in the IEEE standards 802.15.6. for WBAN. In the experiments, customized channel-sounding signals were applied to the human body using a battery-powered device with a ground-electrode size of $27 \times 50$ mm2. The signals received after passage through the body were measured considering 30 kinds of measurement conditions determined by the body postures and locations of the transmitter and receiver. The operating frequencies of the transmission signals were varied up to 100 MHz. This work derives the minimum required lengths of symbol-codes based on analyses of channel-measured data in terms of measurement conditions, operating frequencies, and bandwidths of a receive-filter, to achieve a maximum data rate. This was done to ensure handling of intrinsic signal errors such as those by inter-symbol-interference, and to provide more reliable bit-error-rate performance in the human body channel, depending on the transmitter structures.

본 연구는 청소년 태권도 선수들이 지각하는 지도자의 리더십 유형과 경기력의 관계에서 지도자-선수 교환관계(LMX)의 매개효과를 검증하는 것에 목적이 있으며, 태권도 선수들의 경기력 향상을 위한 기초자료를 제시하고자 하는 것에 연구의 의의가 있다. 이를 위해 고등학교 태권도 선수 341명에게 리더십유형, 지도자-선수 교환관계(LMX), 경기력에 관한 설문자료를 받아 활용하였으며, SPSS 21.0, AMOS 18.0 및 Excel 2010을 사용하여 빈도분석, 신뢰도분석, 확인적 요인분석, 상관관계분석, 구조방정식 모형분석을 실시하였고, 매개효과 유의성은 bootstrapping을 이용하여 검증하였다. 그 결과, 첫째, 태권도 지도자의 리더십 유형은 경기력에 긍정적으로 유의한 영향을 미치는 것으로 나타났다. 둘째, 태권도 지도자의 리더십 유형은 지도자-선수 교환관계 (LMX)에 유의한 영향을 미치는 것으로 나타났다. 셋째, 지도자-선수 교환관계(LMX)는 경기력에 유의한 영향을 미치는 것으로 나타났다. 마지막으로 지도자-선수 교환관계(LMX)는 지도자의 리더십 유형과 경기력의 관계를 완전매개 하는 것으로 나타났다. 이러한 결과를 토대로 태권도 지도자들의 리더십 유형과 경기력, 지도자-선수 교환관계(LMX)에 관하여 논의하였다.

A current reuse (CR) injection-locking frequency divider (ILFD) with low power and wide locking range is proposed. The current reused core is used to decrease the current consumption compared to the conventional ILFD, current-mode logic (CML) and regenerative divider. The fourth-order resonator using a transformer with peaking inductor is employed to overcome narrow locking range of the conventional ILFD. The simulated locking range of the proposed CR-ILFD is from 25.7 to 42.5 GHz at 0-dBm input power and the power consumption of the core is 1.88 mW with 1-V supply voltage. The CR-ILFD was implemented in a 65-nm CMOS technology.

Human body communications (HBC) have been studied as an enabling technology to meet the recently increased demands for low-power and high-simplicity in wireless body area networks for wearable-device applications. Previous works on HBC focused mainly on channel modeling with a measurement method, signal transmission scheme, and transceiver implementation. In particular, the digital transmission, invented as a customized approach for the human body channel, has contributed to develope low-complexity HBC systems. This paper addresses on-going research on capacitive coupling HBC based on digital transmission by exploring recent literature.

A technology for low-power high data-rate digital capsule endoscopy with human body communication (CEHBC) is presented in this paper. To transfer the image data stably with low power consumption, the proposed system uses three major schemes: Frequency selective digital transmission (FSDT) modulation with HBC, the use of an algorithm to select electrode pairs, and the LineSync algorithm. The FSDT modulation supports high-data rate transmission and prevents the signal attenuation effect. The selection algorithm of the electrode pair finds the best receiving channel. The LineSync algorithm synchronizes the data and compensates for data polarity during the long data transmission section between the capsule endoscope and the receiver. Because all the major functional blocks of the CEHBC transmitter can be implemented as digital logics, they can be easily fabricated using the field programmable gate array (FPGA). Moreover, this CEHBC transmitter can achieve low power-consumption and can support a relatively high data rate in spite of using its clock a few tens of MHz slower. The proposed CEHBC-TXD is the digital portion of the CEHBC transmitter that provides low-power (3.7 mW) and high data-rate (6 Mbps) performance while it supports a high-resolution image (480 &times, 480 byte) at 3.13 fps.

In this paper, we propose a fully integrated switched-capacitor DC&ndash, DC converter with low ripple and fast transient response for portable low-power electronic devices. The proposed converter reduces the output ripple by filtering the control ripple via combining a low-dropout regulator with a main switched-capacitor DC&ndash, DC converter with a four-bit digital capacitance modulation control. In addition, the four-phase interleaved technique applied to the main converter reduces the switching ripple. The proposed converter provides an output voltage ranging from 1.2 to 1.5 V from a 3.3 V supply. Its peak efficiency reaches 73% with ripple voltages below 55 mV over the entire output power range. The transient response time for a load current variation from 100 &mu, A to 50 mA is measured to be 800 ns. Importantly, the converter chip, which is fabricated using 0.13 &mu, m complementary metal&ndash, oxide&ndash, semiconductor (CMOS) technology, has a size of 2.04 mm2. We believe that our approach can contribute to advancements in power sources for applications such as wearable electronics and the Internet of Things.

This paper presents an energy management integrated circuit for multiple energy harvesters in wireless body area network applications. The electrical power acquired from a single energy harvester around a human body is limited to micro watts, which is insufficient to drive a wearable electronic device. To increase this small amount, the energy from a number of harvesters has to be combined. By combining the energy from multiple distributed harvesters, each one producing negligible energy, significant energy for wearable devices can be obtained. In designing an energy management circuit for a wearable device, there are two issues to be resolved. The first is related to the power consumption of the circuit, and the second issue is related to the methods needed to manage the wide range of power that occurs as the energy input changes during harvesting. In this paper, an energy management circuit that resolves the two issues above is described. The circuit was integrated using 0.13 &micro, m Taiwan Semiconductor Manufacturing Company complementary metal-oxide-semiconductor technology. The energy management circuit is designed to combine up to three sources of harvested energy with more than 90% operating efficiency over the entire power range of the energy harvested.

A 5-Gb/s/pin transceiver for DDR memory interface is proposed with a crosstalk suppression scheme. The proposed transceiver implements a staggered memory bus topology and a glitch canceller to suppress crosstalk-induced distortions in a memory channel. The transceiver is implemented using 0.18 mum CMOS process and operates at 5 Gb/s. The results demonstrate widened eye diagram and lower bit error rate. The eye width and height of the proposed scheme increases 28.3% and 11.1% compared to the conventional memory transceiver, respectively. The peak-to-peak jitter of output data is 52.82 ps.