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By incorporating Si into AsSeGe system, we demonstrate a 3D stackable OTS+PCM memory in a 1k by 1k cross-point memory array with extremely low $\mathrm{V}_{\mathrm{tS}}$ drift (~0V after 3 days from programming), wide $\mathrm{V}_{\mathrm{tS}}/\mathrm{V}_{\mathrm{tR}}$ window (>2V main distribution memory window), high endurance (>2E11 cycles), excellent $\mathrm{I}_{\mathrm{OFF}}$ and thermal stability. So far, attempts to improve the thermal stability of AsSeGe system sacrifice $\mathrm{I}_{\mathrm{OFF}}$ and cycling endurance. We show that Si incorporation relaxes this trade-off and can greatly improve the thermal stability and cycling endurance while also achieving good $\mathrm{I}_{\mathrm{OFF}}$ . In particular the $\mathrm{I}_{\mathrm{OFF}}$ of AsSeGeSi selector is improved over the AsSeGe system for films of 20 nm.

We present the first MLC operation for OTS-PCM with comprehensive operation algorithm study. An ADM chip with fast write speed ( 10 9 cycles) are shown indicating the potential for high performance MLC OTS-PCM. A desirable 2-bits/cell operation up to 10 8 cycles without further read verification is achieved based on 100 cells data from 1Mbit crosspoint array. Systematic discussions of MLC operation under “1/2V” scheme is further presented, and threshold voltage (Vt) drift is evaluated accordingly.

High endurance ovonic threshold switch (OTS, here, TeAsGeSiSe-based) is integrated with phase change memory (PCM, here, doped Ge2Sb2Te5) to form a 3-D stackable pillar-type device. With the help of an etch buffer layer and a damage-free pillar reactive-ion etching process, we successfully demonstrate one-selector (OTS)/one-resistor (PCM) (1S1R OTS-PCM) pillar device without OTS/PCM composition modification. High temperature 400 °C annealing tests show this 1S1R OTS-PCM pillar device is back end of line compatible. We report the fundamental behavior of the OTS and the operation scheme of the 1S1R OTS-PCM device. The new Vth read scheme is proposed and excellent electrical performance is demonstrated. It provides the fast turn ON/ OFF speed which enables 10-ns fast RESET speed. Program endurance greater than 109 cycles is achieved, and read endurance is higher than 1011 cycles.

We present a scaling study toward lZnm node 3D Cross-point PCM (XPCM) for Storage Class Memory (SCM) applications. The low operation current, and low metal line loading resistance are desired to avoid a wide operation voltage distribution in a cross-point array. For the first time, AC threshold voltage (Vth) of 1S1R OTS-PCM was studied, which will impact the operation scheme. To achieve Tera bits per chip density, six layers 1Znm 3D XPCM with OTS showing high Vth and low leakage current, and scalable periphery circuit are required.

A reliability study for phase change memory (PCM) pillar cell is performed. We found that without a buffer layer, the PCM pillar cell shows earlier endurance failure than its mushroom counterpart, and the underlying failure mechanism is attributed to element segregation. A buffer layer between PCM and top electrode is found to substantially improve the endurance characteristics of the PCM pillar cell to greater than 1E10 program cycles. In addition, the buffer layer also provides the benefit of increased PCM threshold voltage (Vth), which can enlarge the read window margin for the OTS+PCM 3D Cross-Point Memory array.

A reliability study for PCM and OTS intermixing was addressed. The buffer layer between PCM and OTS plays a key role in preventing PCM/OTS intermixing after BEOL processing thermal treatment. Besides cycling endurance, performance degradation due to interlayer intermixing was observed. Optimal device operation and an improved buffer layer allowed drastically improved cycling endurance from a few cycles to > 1E9 cycles.

New selector materials with very-low I OFF and optimum V th . based on As-Se-Ge chalcogenides are studied. An optimized composition is proposed, which achieves a good trade-off between thermal stability and cycling endurance and it is successfully integrated with PCM in a 3D stackable pillar structure. SET/RESET operation are demonstrated with ∼2V memory window. Selector is able to deliver 1mA ON current (7.9 MA/cm2) and fast speed (10 ns). More than 1E12 read cycling endurance is achieved in 1S1R $(\text{OTS}+\text{PCM})$ device due to the excellent endurance of the selector.

For the first time published, high endurance OTS (ovonic threshold switch, here, TeAsGeSiSe-based) is integrated with PCM (here, doped Ge2Sb2Te5) to form a 3D stackable pillar type device. With the help of an etch buffer layer and a damage-free pillar RIE process, we achieved 100% array yield without OTS/PCM composition modification. Anneal tests show this one-selector/one-resistor (1S1R) pillar device is BEOL-compatible.We report excellent electrical performance by 1S1R OTS-PCM device; selector provides the fast turn on/off speed which enables 10ns fast RESET speed, program endurance is 109 cycles, and read endurance is higher than 1011 cycles.

We present the results of a primary study on an OTS chalcogenide material system (TeAsGeSi) that incorporates Se and an extra dopant. Vth and Ioff are trade-off parameters that can be tuned by modification of OTS composition, thickness and process temperature. The resulting new selector material demonstrated excellent endurance (>1010 with 50ns-pulsed 400uA On-current) and robust OTS characteristics after 350°C/30 mins annealing. The thin film could withstand 500 °C annealing.