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This work investigates the impact of boron diffusion under positive bias temperature instability (PBTI) for 16 nm node FinFET high-voltage applications. Boron doped in the extended source/drain region can improve the tolerance of hot carrier stress (HCS). However, boron diffusing into the channel could worsen the interface quality. The shallow defects originating from the diffusive boron would influence the behavior of low-frequency noise (LFN), which is, as a result, unfavorable in terms of CMOS image sensor applications. Therefore, the analysis of the defect behavior is necessary. In this work, a comprehensive inspection including PBTI and LFN is carried out. Boron diffusion may generate shallow interface traps and reflect in PBTI degradation and power spectrum density. At the same time, an abnormal channel length PBTI degradation trend is observed between STD and B/F devices. A complete PBTI model is proposed to figure out the mechanisms. Hence, for high-voltage applications, the investigation may make a better understanding of the impact of defects and suggest solutions.

This study discusses the application of the substrate voltage during the recovery time with the dynamic on-resistance (dynamic ${R}_{\text {on}}$ ) method to extract the deep trap states in the buffer layer after the hard-switching stress in p-GaN high electron mobility transistors (p-GaN HEMTs). This method will be more suitable for the detection of the deep trap states where the carriers are difficult to de-trap in the buffer layer. Then, a hard switching stress condition is applied to the device and the degradation is caused by the mechanism of the hot electron effect and the impact ionization. The generated electrons and holes will trap into the buffer layer in the drift region at the gate edge near the drain side and the AlGaN layer under the gate, respectively. Moreover, through the novel of the dynamic ${R}_{\text {on}}$ method with the substrate voltage applied, the deep trap states in the buffer can be extracted.

In recent years, GaN HEMT has become one of the most ideal devices for its low on-state resistance and high breakdown voltage. Compared with other HEMT structures, GaN MIS HEMT is recognized as one of the most attractive candidates to replace silicon-based high-power devices in the aerospace industry because of their excellent temperature tolerance. Therefore, this study investigates how a wide temperature range of 77–393 K influences the degradation mechanism of negative gate bias stress (NGBS) in GaN MIS-HEMTs. The threshold voltage shift for GaN MIS-HEMTs’ NGBS is very distinctive both under cryogenic temperature and high temperature. Typically, as the temperature rises from 77 to 303 K, the positive shift of threshold voltage also increases due to electron trapping in the Si3N4 bulk layer and at the Si3N4/AlGaN interface. However, from 303 to 393 K, the opposite behavior of the threshold voltage shift is observed due to additional hole trapping in Si3N4 from ionization impact, which can be verified from its stress data in Silvaco TCAD simulation and its recovery duration as well. In addition, a thicker Si3N4 layer device is produced to clarify the NGBS model. Thus, this study proposes an extensive NGBS model from 77 to 393 K to verify the abnormal degradation phenomenon in GaN MIS-HEMTs.

This study examines the impact of supercritical fluid treatment on 1200V 4H-SiC vertical double diffusion MOSFETs (VD-MOSFETs). When exposed to pure carbon dioxide or carbon dioxide mixed with nitrous oxide, there is a significant increase in the improvement ratio of drain current, which is contingent upon channel mobility but has no effect on threshold voltage. Conversely, the degradation of drain current caused by ammonia gas treatment is attributed to a reduction in channel mobility. Furthermore, the treatment with pure carbon dioxide or carbon dioxide mixed with nitrous oxide effectively passivates shallow defects, while the presence of hydrogen atoms in ammonia gas leads to an increase in shallow defects.

In this study, negative gate bias stress (NGBS) is applied to the Si3N4 metal–insulator–semiconductor high electron mobility transistors (MIS-HEMTs). The gate electron injected into the Si3N4 dielectric layer and the holes generated by the impact ionization trapped into the AlGaN layer are the two main degradation mechanisms, which cause the unstable threshold voltage. Moreover, it is discovered that an abnormal ${C}$ – ${V}$ hump is generated after NGBS because of the uneven hole trapping at the AlGaN near the channel under the gate. The unusual direction of the electric field, which is related to the mesa isolation technology, is observed under NGBS condition in the Silvaco TCAD simulation. The location of the hole trapping is verified by the positive gate bias after NGBS during the recovery time. Finally, the device without the mesa isolation is used to verify the abnormal degradation results.

In this study, the reliability issues are discussed under dc and ac negative gate bias stress (ac-NGBS) in Al2O3/Si3N4 metal–insulator–semiconductor high electron mobility transistors (MIS-HEMTs). Converse degradation between these two stress conditions is discovered. The holes generated by trap-assisted thermionic field emission (TA-TFE) are trapped into the Al2O3 layer, so that the threshold voltage ( ${V}_{\text {th}}$ ) decreases under dc negative gate bias stress (dc-NGBS). ${V}_{\text {th}}$ increases because of the hot electrons injected into the GaN layer, while the device is turned on quickly under ac-NGBS. In addition, the degradation mechanisms under dc-NGBS and ac-NGBS are confirmed by the OFF-state gate and drain leakages, respectively. Silvaco TCAD is used to validate the degradation mechanism under ac-NGBS. Finally, the characteristics of the ${V}_{\text {th}}$ shift transition from dc to ac NGBS are discussed.

In this work, the issue of abnormal two-stage hot carrier injection (HCI) degradation in n-type lateral double-diffused MOS (LDMOS) transistors is explored. The degradation mechanism is divided into two stages. The first stage is the electron injection into the interface layer (IL) caused by the impact ionization that occurs under the contact field plate (CFP), resulting in the degradation of the ON-current ( ${I}_{\text {on}}{)}$ . The second stage of deterioration is the positive bias temperature instability (PBTI) effects caused by Joule heating, which leads to defects in the SiO2/Si interface, and injects electrons in the channel into SiO2, which increases the subthreshold swing (S.S) of the device and causes the threshold voltage ( ${V}_{\text {th}}{)}$ to shift. It has been proved by temperature variation experiments and technology computer-aided design (TCAD) simulations that HCI will indeed produce severe PBTI effects and lead to device degradation during long-term HCI.

In this study, X-ray irradiation of metal–insulator–semiconductor (MIS) AlGaN/GaN high-electron-mobility transistors (HEMTs) is performed. After the X-ray irradiation, the threshold voltage ( ${V}_{\text {th}}{)}$ shift and ON-state current ( ${I}_{\text {on}}{)}$ variation are observed. However, after a recovery period, the degradation trend of ${V}_{\text {th}}$ and that of ${I}_{\text {on}}$ are in opposite directions. Such opposite degradations are demonstrated and explained in this study. As X-rays irradiate the devices, holes, and defects are generated in the GaN layer and Si3N4 layer, respectively. To prove the degradation mechanism induced by X-rays in MIS HEMT, the following characteristics are offered. The drain current ( ${I}_{d}{)}$ and the source current ( ${I}_{s}{)}$ under the X-ray irradiation are introduced to prove the hole generation. The two-step degradation of the gate current ( ${I}_{g}{)}$ after X-ray irradiation provides evidence of the formation of defect states. Moreover, the different degradation behaviors between Schottky-gate HEMT and MIS HEMT are compared and verification of the position of generation of defect states in the Si3N4 layer is given accordingly.