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This article presents the design of a dual-mode V-band power amplifier (PA) that enhances the efficiency at power back-off (PBO) using load modulation. The PA utilizes a reconfigurable two-/four-way power combiner to enable two discrete modes of operation–full power and back-off power. The power combiner employs two techniques to further improve the PA efficiency at PBO: 1) usage of transformers with non-uniform turns ratios to reduce the difference in impedance presented to the PA cores between the two modes and 2) utilize a proposed switching scheme to eliminate the leakage inductance associated with the disabled path in back-off power mode (BPM). The two-stage PA achieves a peak gain of 21.4 dB with a fractional BW (fBW) of 22.6% (51–64 GHz). At 65 GHz, the PA has a Psat of +17.9 dBm with an OP1 dB of +13.5 dBm and a peak power added efficiency (PAE) of 26.5% in full-power mode. In BPM, the measured Psat, OP1 dB, and peak PAE are +13.8 dBm, +9.6 dBm, and 18.4%, respectively. The PAE is enhanced by 6% points at a 4.5-dB back-off. The PA is capable of amplifying a 6 Gb/s 16-QAM modulated signal with an EVMrms of −20.7 dB at an average Pout/PAE of +13 dBm/13.6%, respectively. This PA was implemented in 16-nm FinFET, occupies a core area of 0.107 mm2, and operates under a 0.95-V supply.

Integration of discrete radios onto a single-silicon CMOS substrate [1]-[6], followed by commercialization of single-chip cellular, Bluetooth, and Wi-Fi radios [7]-[9], has shaped the wireless world that we live in today. Although integration of wireless transceivers with powerful microprocessors in very large systems on chip (SoCs) is currently commonplace in consumer electronics, the demand for lower power consumption, higher effective data rates, and higher network capacity continues to drive research on integrated radios. By some estimates, the demand for mobile data per volume area will increase 1,000x during the next decade, with end-user data rates increasing by as much as 10-100x [10].

This paper presents the design of a dual-mode V-band PA with efficiency enhancement at power back-off via load modulation. The design utilizes a reconfigurable 2/4-way non-uniform power combiner to enable two discrete modes of operation – full power and back-off power. The 2-stage PA achieves a peak gain of 21.4dB with a fractional BW of 22.6% (51-64GHz). At 65GHz, the PA has a P sat of +17.9dBm with an OP 1dB of +13.5dBm and a peak PAE of 26.5% in full-power mode. In back-off power mode, the measured P sat , OP 1dB , and peak PAE are +13.8dBm, +9.6dBm, and 18.4%, respectively. The PAE is enhanced by 6-% points at 4.5-dB back-off. The PA is capable of amplifying a 6-Gb/s 16-QAM modulated signal with an EVM rms of -20.7dB at an average P out /PAE of +13dBm/13.6%, respectively. This PA is implemented in 16-nm FinFET, occupies a core area of 0.107mm2, and operates under a 0.95-V supply.

This paper provides an overview of both the challenges and the current state-of-the-art in the areas of full duplex (FD) and frequency division duplex (FDD) integrated transceivers. Implementation hurdles in the form of the linearity, noise, bandwidth (BW) and power of transmitter (TX) self-interference (SI) cancellation circuitry are explored. The difficulty of performing SI cancellation is heavily influenced by the modulation method, the maximum TX power output and the receiver (RX) BW. This paper highlights some recent implementation examples of single-chip FD radios that range in performance from low-power cancellation techniques, to transceivers which target broad channel BW (>40MHz) using high output power transmitters. Several 40nm CMOS devices which range in performance from a narrowband low-energy Bluetooth transceiver to analog-frontends which integrate a +24dBm power amplifier (PA) with a dual-point feedforward cancellation architecture for broadband and deep SI suppression are discussed.

This paper presents a fully integrated dual-antenna phased-array RF front-end receiver architecture for 60-GHz broadband wireless applications. It contains two differential receiver chains, each receiver path consists of an on-chip balun, agm-boosted current-reuse low-noise amplifier (LNA), a sub-harmonic dual-gate down-conversion mixer, an IF mixer, and a baseband gain stage. An active all-pass filter is employed to adjust the phase shift of each LO signal. Associated with the proposed dual conversion topology, the phase shift of the LO signal can be scaled to one-third. Differential circuitry is adopted to achieve good common-mode rejection. The gm-boosted current-reuse differential LNA mitigates the noise, gain, robustness, stability, and integration challenges. The sub-harmonic dual-gate down-conversion mixer prevents the third harmonic issue in LO as well. Realized in a 0.13-mum 1P8M RF CMOS technology, the chip occupies an active area of 1.1 times 1.2 mm2. The measured conversion gain and input P1 dB of the single receiver path are 30 dB and -27 dBm , respectively. The measured noise figure at 100 MHz baseband output is around 10 dB. The measured phased array in the receiver achieves a total gain of 34.5 dB and theoretically improves the receiver SNR by 4.5 dB. The proposed 60 GHz receiver dissipates 44 mW from a 1.2 V supply voltage. The whole two-channel receiver, including the vector modulator circuits for built-in testing, consumes 93 mW from a 1.2 V supply voltage.

A low-power gigabits FSK demodulator using injection-locked technique is employed for 60GHz wireless communication systems. Compared with the conventional LC tank discriminator, the injection-locked oscillator provides a stable frequency-to-phase transformation for analog non-coherent FSK demodulation. Fabricated in 0.13-µm CMOS technology, this FSK demodulation only occupies a chip area of 0.5×0.45mm 2 . The measured data rate and the detecting range of the injection-locked FSK demodulator are 2.5Gbps and ±1GHz respectively. The demodulation input sensitivity is -16dBm at BER less than 10 −9 for uncoded 2.5Gbps 2 31 -1 PRBS data with 1GHz frequency deviation while consuming 6mW from a 1.2V supply.

This paper presents a fully differential receiver with on-chip baluns for 60 GHz broadband wireless applications. This design consists of on-chip baluns, gm-boosted current-reuse low-noise amplifier (LNA), sub-harmonic dual-gate down conversion mixer, second IF mixer and baseband gain stage. Fully differential circuit technique is adopted to obtain good common mode performance. The gm-boosted current-reuse differential LNA mitigates the noise, gain, robustness, stability, and integration issues associated with previous solutions. The sub-harmonic dual-gate down conversion mixer prevents the issue of the third harmonic of the LO as well. The measured conversion gain and input P1dB of the proposed receiver are 30 dB and -27 dBm, respectively. The measured noise figure at 100 MHz baseband output is around 10 dB. The proposed 60 GHz receiver dissipates 44 mW with a 1.2 V supply voltage. The fully differential receiver with the on-chip baluns is implemented in a standard 0.13 mum 1P8M+ RF CMOS technology.