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In this work, 10 and 20 nm diameter colloidal CdSe nanowires (NWs) have been successfully incorporated into ZnSe layers grown by molecular beam epitaxy on GaAs substrates. Atomic force microscopy and scanning electron microscopy were carried out to study the surface morphology of the samples. Transmission electron microscopy and energy-dispersive x-ray analysis were also carried out to study the chemical composition and lattice structure around the embedded CdSe NWs. Finally, single NW photoluminescence (PL) spectroscopy and PL imaging were used to study the optical properties of ZnSe films containing CdSe NWs. The experimental results confirm the presence of embedded CdSe NWs in the ZnSe films and show that the embedded NWs remain optically active [ABSTRACT FROM AUTHOR]

We have formulated a geometric non-linear mathematical-physical model of the snap-through of the system of a thin-walled shallow bimetallic translation shell in a homogenous temperature field according to the theory of large displacements, moderate rotations, and small strains of the shell element. The model enables the calculation of the geometric conditions, of shallow translation shells, due to the influences of temperature and mechanical loads. The results are based on the numeric solution of a non-linear system of partial differential equations with boundary conditions according to the finite difference method. [ABSTRACT FROM AUTHOR]

Vertical n-channel tunnel field-effect transistors (TFETs) with tunneling normal to the gate based on an n+ In∞=0.53->;1GaAs/p+ InP heterojunction have been demonstrated to exhibit simultaneously a high ION/IOFF ratio of 6 × 105, a minimum subthreshold swing (SS) of 93 mV/dec, and an on-current of 20 μA/μm at VDS = 0.5 V and a gate swing of 1.75 V at 300 K, a record TFET performance. The significant improvement in device performance is ascribed to the adoption of a thin equivalent oxide thickness (EOT) of ~1.3 nm for improved electrostatics and the use of plasma-enhanced chemical vapor deposition SiN∞ mesa passivation to preserve the integrity of the thin exposed semiconductor layers. [ABSTRACT FROM AUTHOR]

This paper reports the first demonstration of a microwave-frequency operation of a GaAs MOSFET fabricated using a wet thermal oxidization of InAIP lattice-matched to GaAs to form a native-oxide gate insulator. Devices with 1-μm gate lengths exhibit a cutoff frequency (ft) of 13.7 GHz and a maximum frequency of oscillation (fmax) of 37.6 GHz, as well as a peak extrinsic transconductance of 73.6 mS/mm. A low-leakage current density of 3.8 × 10³cm² at 1-V bias for an MOS capacitor demonstrates the good insulating properties of the ∼ 1-nm thick native gate oxide. [ABSTRACT FROM AUTHOR]