173 results on '"Koji Nii"'
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2. A 3nm Fin-FET 19.87-Mbit/mm2 2RW Pseudo Dual-Port 6T SRAM with High-R Wire Tracking and Sequential Access Aware Dynamic Power Reduction.
3. 3.7-GHz Multi-Bank High-Current Single-Port Cache SRAM with 0.5V-1.4V Wide Voltage Range Operation in 3nm FinFET for HPC Applications.
4. A 3-nm 27.6-Mbit/mm2 Self-timed SRAM Enabling 0.48 - 1.2 V Wide Operating Range with Far-end Pre-charge and Weak-Bit Tracking.
5. A Cost-Effective Embedded Nonvolatile Memory with Scalable LEE Flash®-G2 SONOS for Secure IoT and Computing-in-Memory (CiM) Applications.
6. 40-nm 64-kbit Buffer/Backup SRAM with 330 nW Standby Power at 65°C Using 3.3 V IO MOSs for PMIC less MCU in IoT Applications.
7. A dynamic power reduction in synchronous 2RW 8T dual-port SRAM by adjusting wordline pulse timing with same/different row access mode.
8. FEOL/BEOL wear-out estimator using stress-to-frequency conversion of voltage/temperature-sensitive ring oscillators for 28nm automotive MCUs.
9. A 5.92-Mb/mm2 28-nm pseudo 2-read/write dual-port SRAM using double pumping circuitry.
10. Low-power multi-sensor system with task scheduling and autonomous standby mode transition control for IoT applications.
11. An on-die digital aging monitor against HCI and xBTI in 16 nm Fin-FET bulk CMOS technology.
12. A cost effective test screening method on 40-nm 4-Mb embedded SRAM for low-power MCU.
13. A 298-fJ/writecycle 650-fJ/readcycle 8T three-port SRAM in 28-nm FD-SOI process technology for image processor.
14. 40 nm Dual-port and two-port SRAMs for automotive MCU applications under the wide temperature range of -40 to 170°C with test screening against write disturb issues.
15. The LSI implementation of a memory based field programmable device for MCU peripherals.
16. A 40-nm resilient cache memory for dynamic variation tolerance with bit-enhancing memory and on-chip diagnosis structures delivering ×91 failure rate improvement.
17. 40nm Ultra-low leakage SRAM at 170 deg.C operation for embedded flash MCU.
18. Assessing uniqueness and reliability of SRAM-based Physical Unclonable Functions from silicon measurements in 45-nm bulk CMOS.
19. 12-NM Fin-FET 3.0G-Search/s 80-Bit × 128-Entry Dual-Port Ternary CAM.
20. A Fully Standard-Cell Based On-Chip BTI and HCI Monitor with 6.2x BTI sensitivity and 3.6x HCI sensitivity at 7 nm Fin-FET Process.
21. Disturbance Aware Dynamic Power Reduction in Synchronous 2RW Dual-Port 8T SRAM by Self-Adjusting Wordline Pulse Timing
22. Testability improvement for 12.8 GB/s Wide IO DRAM controller by small area pre-bonding TSV tests and a 1 GHz sampled fully digital noise monitor.
23. A 28nm high density 1R/1W 8T-SRAM macro with screening circuitry against read disturb failure.
24. A cost-effective 45nm 6T-SRAM reducing 50mV Vmin and 53% standby leakage with multi-Vt asymmetric halo MOS and write assist circuitry.
25. A 123μW standby power technique with EM-tolerant 1.8V I/O NMOS power switch in 28nm HKMG technology.
26. A Test Screening Method for 28 nm HK/MG Single-Port and Dual-Port SRAMs Considering with Dynamic Stability and Read/Write Disturb Issues.
27. Quasi-Planar Tri-gate (QPT) bulk CMOS technology for single-port SRAM application.
28. A stable chip-ID generating physical uncloneable function using random address errors in SRAM.
29. A dynamic body-biased SRAM with asymmetric halo implant MOSFETs.
30. Dynamic stability in minimum operating voltage Vmin for single-port and dual-port SRAMs.
31. A 28 nm 50% power reduced 2T mask ROM with 0.72 ns read access time using column source bias.
32. Study of impact of BTI's local layout effect including recovery effect on various standard-cells in 10nm FinFET.
33. Dependable SRAM with enhanced read-/write-margins by fine-grained assist bias control for low-voltage operation.
34. A 0.56-V 128kb 10T SRAM using column line assist (CLA) scheme.
35. Cost-Effective Test Screening Method on 40-nm Embedded SRAMs for Low-Power MCUs
36. A 10T Non-Precharge Two-Port SRAM for 74% Power Reduction in Video Processing.
37. A 65nm Embedded SRAM with Wafer-Level Burn-In Mode, Leak-Bit Redundancy and E-Trim Fuse for Known Good Die.
38. A 45nm Low-Standby-Power Embedded SRAM with Improved Immunity Against Process and Temperature Variations.
39. A two-port SRAM for real-time video processor saving 53% of bitline power with majority logic and data-bit reordering.
40. Worst-case analysis to obtain stable read/write DC margin of high density 6T-SRAM-array with local Vth variability.
41. A 32×24-bit multiplier-accumulator with advanced rectangular styled Wallace-tree structure.
42. A 6.05-Mb/mm2 16-nm FinFET double pumping 1W1R 2-port SRAM with 313 ps read access time.
43. A 28nm 360ps-access-time two-port SRAM with a time-sharing scheme to circumvent read disturbs.
44. A low power SRAM using auto-backgate-controlled MT-CMOS.
45. A 512-kb 1-GHz 28-nm partially write-assisted dual-port SRAM with self-adjustable negative bias bitline.
46. 13.3 20nm High-density single-port and dual-port SRAMs with wordline-voltage-adjustment system for read/write assists.
47. 10.2 A 28nm HPM heterogeneous multi-core mobile application processor with 2GHz cores and low-power 1GHz cores.
48. 13.6 A 28nm 400MHz 4-parallel 1.6Gsearch/s 80Mb ternary CAM.
49. LSSD Compatible and Concurrently Testable Ram.
50. A parameter adjustment method for analog circuits based on convex fuzzy decision using constraints of satisfactory level.
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