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A novel method for selective deposition of metal features has been developed and evaluated for several different metallization applications in device manufacturing and advanced packaging technologies. Selectroplating® is based on a selective chemical modification (SCM) of field areas of a wafer and can be implemented for either a fill-based integration, such as Cu dual damascene, or an additive process such as plating of wide conductive lines. In either integration, the primary benefit of selective deposition is to prevent deposition of metal in areas between desired features thus eliminating the need to remove excess bulk metal in the next step.

Thin film deposition of metals is necessary in the fabrication sequence of most electronic devices, but much of the deposited metal is actually wasted in the subsequent patterning steps. In the case of copper interconnects for advanced semiconductor chips, a blanket layer of Cu is electroplated over the entire wafer to fill tiny trenches etched into a dielectric layer, then all of the metal in the field areas is removed by chemical mechanical planarization (CMP). In other devices, the conductive layer may be aluminum or some other metal, and the patterning may be based on photo and etch steps, but in nearly all cases, a large percentage of the initial metal is removed and sent down the drain or out the process gas exhaust. In recent years, packaging technologies and MEMS devices have adopted similar processes for metal layers, many of which involve even thicker layers and even more wasted metal. In all of these process sequences, substantial savings could be realized if the metal could be deposited in a selective manner and focused primarily into the features of interest rather than depositing a blanket layer.A novel method for selective deposition (Selectroplating®) has been developed and evaluated for several such metallization applications. This technology is based on a selective chemical modification (SCM) of field areas of a wafer and can be implemented for either a fill-based integration, such as Cu dual damascene, or an additive process such as plating of wide conductive lines. In either integration, the primary benefit of selective deposition is to prevent metal from being deposited in areas between desired features thus eliminating the need to remove excess bulk in the next step. Cost savings is realized in two ways: 1) less metal is consumed from the plating bath thus extending bath life and lowering the average deposition cost, and 2) substantially less bulk metal must be removed in the subtractive step which lowers the polish or etch time. This improves throughput and further decreases cost.

Chemical Mechanical Planarization is more than ever a key technology, not only in advanced CMOS fabrication but also in emerging areas like the “Internet Of Things” (IOT). Whereas lower nm-CMOS-nodes require a perfect process control with nearly zero within-wafer-non-uniformity, “atomic layer CMP”, IOT applications introduce an almost unlimited number of new and partly contradictory process demands. “Crazy” layouts are accompanied by various substrate diameters and thicknesses. The list of materials, which need to be planarized, is almost as long as the periodic table of elements. On the other hand, the requirements on planarity and surface quality are not much less challenging than for advanced CMOS. All that comes along with a modest number of wafers. In conclusion, IOT device fabrication needs highly flexible CMP setups, which ensure a process quality and performance comparable to advanced CMOS fabrication. Actually, this is needed not only for fabrication but also for any process development and research in this field. How to deal with this situation? State of the art CMP equipment will certainly give the desired process quality, however, it is mostly dedicated to high throughput at specific process settings. One advantage of modern equipment is that advanced membrane heads are very forgiving when it comes to wafer thickness variation. The capability to handle substrate sizes with a reasonable conversion effort, however, is limited. Moreover, these machines are tremendously expensive in procurement and operation. Even refurbished equipment of a recent generation will only partially solve this problem. For research facilities like Fraunhofer, and probably for some small and medium IOT device manufactures, such tools are not a viable option financially. Against this background, depreciated legacy tools become an interesting alternative. The market is filled with this type of equipment. Refurbishing companies, often specialized to these machines, are able to give them a second life. The major issue: How to achieve the necessary process performance with reasonable conversion effort? In order to achieve exactly that, the equipment needs to be upgraded with state of the art/advanced options, such as advanced membrane polish heads (carriers). Within this paper we will present process results obtained from a remanufactured IPEC CMP tool, equipped with advanced membrane carriers. The necessary tool modification comprises a complete reconstruction of polish arm inner workings as well as new hardware and software to control the carrier, which will be briefly explained. As a result of this work, the tool is made able to work with 150 mm and 200 mm membrane carriers without tremendous conversion effort. Running the equipment in manual or semi automatic mode, as usually done in research and development environments, requires less than 15 minutes for a diameter change. For CMP of dielectric, Figure 1 shows that the upgraded head produces not only better non-uniformity for 200mm wafers, but also opens up the process parameter window to allow for improved removal rate as well. In addition, a 100mm membrane carrier has been recently developed. This carrier enables for the first time the advanced process capability of CMP for the 100mm non-Si wafers being used for the development of many novel devices. Figure 2 demonstrates that the non-uniformity, removal rate, and profile tunability of advanced carriers is now available for 100mm wafers. The main objective of this paper is to work out important process characteristics, such as within wafer non-uniformity and reproducibility. To that, a series of experiments was carried out and will be explained in detail.Based on the result we will discuss opportunities and limitations of such a tool modification. Finally, we will give selected application examples. Figure 1

This paper investigates the influence of CH"4, NH"3, H"2 and He plasma on properties of porous low-k film and its effects on resisting moisture absorption during CMP and ions penetration from sputtering. It is found that the H"2, He, NH"3 plasma can cause aggressive carbon depletion in the porous low-k films and change the low-k surface from hydrophobic to hydrophilic, which will induce moisture uptake into the low-k material during the CMP process, and result in increase of the k value and leakage current density. The CH"4 plasma can make low-k material more resist against moisture uptake and keep the k value stable and a good electrical property of the low-k films.

Technologies for the 3D integration are described within this paper with respect to devices that have to retain a specific minimum wafer thickness for handling purposes (CMOS) and integrity of mechanical elements (MEMS). This implies Through-Silicon Vias (TSVs) with large dimensions and high aspect ratios (HAR). Moreover, as a main objective, the aspired TSV technology had to be universal and scalable with the designated utilization in a MEMS/CMOS foundry. Two TSV approaches are investigated and discussed, in which the TSVs were fabricated either before or after wafer thinning. One distinctive feature is an incomplete TSV Cu-filling, which avoids long processing and complex process control, while minimizing the thermomechanical stress between Cu and Si and related adverse effects in the device. However, the incomplete filling also includes various challenges regarding process integration. A method based on pattern plating is described, in which TSVs are metalized at the same time as the redistribution layer and which eliminates the need for additional planarization and patterning steps. For MEMS, the realization of a protective hermetically sealed capping is crucial, which is addressed in this paper by glass frit wafer level bonding and is discussed for hermetic sealing of MEMS inertial sensors. The TSV based 3D integration technologies are demonstrated on CMOS like test vehicle and on a MEMS device fabricated in Air Gap Insulated Microstructure (AIM) technology.

Dielectric stacks containing porous low-k materials were investigated regarding their ability to pass CMP processes as used in Cu interconnect technology. Beside the low-k material itself, the impact of layout, cap layer materials and different diffusion barrier materials has been proven. Advanced consumables, partly specially designed for future technology nodes, have been tested within these experiments. Compatibility of the slurries with the low-k stacks, dishing and erosion, impact of polishing parameters like down force and platen speed on low-k stack integrity were examined. Low-k stacks based on a porous MSQ material capped with PECVD-SiC or with a MSQ-hard mask were found to be promising candidates. Low-k stacks based on porous SiO"2-aerogel could not meet the stability requirements at present and need additional efforts for adhesion enhancement between cap layer and porous material. Consumables used within the experiments enable an efficient processing with low dishing and erosion as well as an excellent surface quality.

Mit dem vorgestellten Sensor ist die Vollstrommessung von CO, THC und NOx unmittelbar im Abgasstrang von Kraftfahrzeugen moglich. Das Messsystem besteht aus einem Titanoxidgassensorarray und der Mess-, Steuer- und Auswerteelektronik. Es erfolgten umfangreiche experimentelle Untersuchungen an Otto- und Dieselmotoren. An dem vom Freistaat Sachsen geforderten Projekt waren u.a. GPP Chemnitz mbH, ZfM der TU Chemnitz, ZAFT e.V. an der HTW Dresden und ZMD AG Dresden beteiligt.

The applications of inertial sensors have a wide variety in terms of accuracy and costs. A new technology approach is joining higher sensor accuracy and lower production costs by using a new Interposer / sensor interconnect technology applied on 300 mm wafer diameter without changing the sensor element itself. The higher accuracy is mainly covered by a multiple point program: (1) stress less assembly due interface silicon Interposer to silicon MEMS; (2) better Signal to Noise Ratio (SNR) by polymer redistribution layer on the interposer (due to better wiring geometry and less parasitic capacities / inductivities); (3) reduction of mechanical stress by using flexible bar springs for mechanical decoupling of sensor and Interposer substrate; (4) additional stress reduction by using a polymer layer for mechanical decoupling of metal redistribution layer (RDL) and Interposer substrate. The cost efficiency even in small scale serial production based on: (1) 300 mm multi project wafer technology including warehouse ready system packaging; (2) a new MEMS contact technology, which gives technical benefit, smaller dimensions and simplifies the assembly of MEMS and ASIC (which are placed on a 2.5D-Interposer in order to enable a System In Package (SiP) as well as for higher sensor accuracy); (3) the flexible ASIC feature enables the integration of different MEMS with analogue signal output; (4) minor costs for integration of different sensors into the existing package. The heterogeneous 3D integration is a key enabler and justifies the additional process steps (mainly TSV-processing, thin wafer handling) by implementing the advantages of the polymer RDL. This integration approach results leads to improved mechanical and electrical properties. This paper will give an overview about the current achievements in the SIMEIT-project, which are predestined to improve the accuracy of different MEMS-applications with analogue signal transfer to the ASIC as well as MEMS-applications with need of stress less integration.

The present study is focused on the development of a gas sensor for application in a high temperature environment. The sensor has been realised using thin films prepared on silicon substrates including a high temperature stable heating and wiring system. TiO2 acts as sensitive layer. Measurements have been carried out in synthetic gas mixtures as well as in gases in a given application. Neural networks and multivariate data analysis have been used for determining the gas concentrations. The capability to detect CO, NO x , and toluene is shown.

For considerations of stress reduction HAR-TSVs were only partially filled with copper. A comparison was made to ring shaped TSVs (i.e. copper ring with silicon core). Two approaches regarding the way of TSV implementation (before and after wafer bonding/ thinning, resp.) are discussed, concerning process ability and yield aspects. Electrical measurement yield 11 MΩ for a single TSV and 76 MΩ for a 4-point TSV-chain (incl. RDL).

The prototype of an exhaust gas sensor presented in this article is capable of performing full stream measurements within the exhaust pipe of internal combustion engines. The measurement system consists of a metal oxide gas sensor array and a control unit for sensor temperature control, sensor signal recording and data analysis. Extensive experimental work was carried out with gasoline and diesel engines on engine test benches. The project, supported by the State of Saxony, was performed by GPP Chemnitz mbH, ZfM at the Free TU Chemnitz, ZAFT e.V. at HTW Dresden and ZMD AG Dresden.

The influence of CH 4 , H 2 , NH 3 and He plasma on the properties of porous low-k material is studied. It is found that the H 2 , He, NH 3 plasma can cause huge carbon depletion in the porous low-k material, and change the low-k surface from hydrophobic to hydrophilic, which will induce moisture uptake into the low-k material during the CMP process, and results in the increase of the k value and leakage current. The CH 4 plasma can make low-k material more resist against moisture uptake and keep the k value and leakage current of low-k films stable.

One limiting parameter for the application of MEMS in cars at places with elevated temperatures is the interconnect and wiring system of these devices. Currently used materials and technological concepts often are not sufficient for temperatures far above 125°C. This article attempts at first, to reflect main problems of device metallization at high temperatures. Finally, two application specific interconnect and wiring concepts are briefly introduced, which are able to work at temperatures up to 400°C and up to 500°C, respectively.

Silicon is the dominating material for the fabrication of MEMS devices, especially in high volume production. However, metals with their typical properties are used to enhance or enable the functionality of MEMS. In contrast to microelectronic technologies, not only the electrical but also the mechanical and optical behavior of metals could be helpful. New requirements in MEMS technologies demand optimized processes in metallization for the fabrication of microstructures.This paper presents some metallization applications and related technology development in the field of MEMS.