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The TAROGE-M observatory is an autonomous antenna array on the top of Mt. Melbourne (∼2700 m altitude) in Antarctica, designed to detect radio pulses from ultra-high energy (over 1017 eV) air showers coming from near-horizon directions. The targeted sources include cosmic rays, Earth-skimming tau neutrinos, and most of all, the anomalous near-horizon upward-going events of yet unknown origin discovered by ANITA experiments. The detection concept follows that of ANITA: monitoring large area of ice from high-altitude and taking advantage of strong geomagnetic field and quiet radio background in Antarctica, whereas having significantly greater livetime and scalability. The TAROGE-M station, upgraded from its prototype built in 2019, was deployed in January 2020, and consists of 6 log-periodic dipole antennas pointing horizontally with bandwidth of 180-450 MHz. The station is then calibrated with drone-borne transmitter, with which the event reconstruction obtained ∼0.3° angular resolution. The station was then smoothly operating in the following month, with the live time of ∼ 30 days, before interrupted by a power problem, and its online filtering has identified several candidate cosmic-ray events and sent out via satellite communication. In this paper, the instrumentation of the station for polar and high-altitude environment, its radio-locating performance, the preliminary result on cosmic-ray detection, and the future extension plan are presented.

TAROGE-M is a self-triggered radio antenna array atop the 2700 m high Mt.Melbourne in Antarctica, designed to detect impulsive geomagnetic emission fromextensive air showers induced by ultra-high energy (UHE) particles beyond 0.1EeV, including cosmic rays (CRs), Earth-skimming tau neutrinos, andparticularly, the "ANITA anomalous events" (AAEs) from near and below thehorizon, which origin remains uncertain and requires more experimental inputsfor clarification. The detection concept of TAROGE-M takes advantage of a high altitude withsynoptic view toward the horizon as an efficient signal collector, and theradio quietness as well as strong and near vertical geomagnetic field inAntarctica. This approach has a low energy threshold, high duty cycle, and iseasy to extend for quickly enlarging statistics. Here we report experimentalresults from the first TAROGE-M station deployed in 2020, corresponding to$25.3$-days of livetime. The station consists of six receiving antennasoperating at 180-450 MHz, and can reconstruct source directions with$\sim0.3^\circ$ angular resolution. To demonstrate its ability to detect UHEair showers, a search for CR signals in the data was conducted, resulting inseven identified events. These events have a mean reconstructed energy of$0.95_{-0.31}^{+0.46}$ EeV and zenith angles between $25^\circ-82^\circ$, withboth distributions agreeing with simulations. The estimated CR flux is alsoconsistent with results of other experiments. The TAROGE-M sensitivity to AAEsis approximated by the tau neutrino exposure with simulations, suggestingcomparable sensitivity as ANITA's at $~1$ EeV energy with a few station-yearsof operation. These first results verified the station design and performancein a polar and high-altitude environment, and are promising for furtherdiscovery of tau neutrinos and AAEs after an extension in the near future.

The design and performance of a multi-G-sample/s fully-synchronous analogtransient waveform recorder I.C. ("SST") with fast and flexible triggercapabilities is presented. Containing 4 channels of 256 samples per channel andfabricated in a 0.25 {\mu}m CMOS process, it has a 1.9V input range on a 2.5Vsupply, achieves 12 bits of dynamic range, and uses ~160 mW while operating at2 G-samples/s and full trigger speeds. With a standard 50 Ohm input source, theSST's analog input bandwidth is ~1.3 GHz within about +/-0.5 dB and reaches a-3 dB bandwidth of 1.5 GHz. The SST's internal sample clocks are generatedsynchronously via a shift register driven by an external LVDS oscillator,interleaved to double its speed (e.g., a 1 GHz clock yields 2 G-samples/s). Itcan operate over 6 orders of magnitude in sample rates (2 kHz to 2 GHz). Onlythree active control lines are necessary for operation: Reset, Start/Stop andRead-Clock. Each of the four channels integrates dual-threshold discriminationof signals with ~1 mV RMS resolution at >600 MHz bandwidth. Comparator resultsare directly available for simple threshold monitoring and rate control. TheHigh and Low discrimination can also be AND'd over an adjustable window of timein order to exclusively trigger on bipolar impulsive signals. Trigger outputscan be CMOS or low-voltage differential signals, e.g. 1.2V CMOS or positive-ECL(0-0.8V) for low noise. After calibration, the imprecision of timingdifferences between channels falls in a range of 1.12-2.37 ps sigma at 2G-samples/s.

A monolithic multi-channel analog transient recorder, implemented usingswitched capacitor sample-and-hold circuits and a high-speedanalogically-adjustable delay-line-based write clock, has been designed,fabricated and tested. The 2.1 by 6.9 mm layout, in 1.2 micron CMOS, includesover 31,000 transistors and 2048 double polysilicon capacitors. The circuitcontains four parallel channels, each with a 512 deep switched-capacitorsample-and-hold system. A 512 deep edge sensitive tapped active delay line useslook-ahead and 16 way interleaving to develop the 512 sample and hold clocks,each as little as 3.2 ns wide and 200 ps apart. Measurements of the device havedemonstrated 5 GHz maximum sample rate, at least 350 MHz bandwidth, anextrapolated rms aperture uncertainty per sample of 0.7 ps, and a signal to rmsnoise ratio of 2000:1.

Radio-glaciological parameters from the Moore's Bay region of the Ross Ice Shelf, Antarctica, have been measured. The thickness of the ice shelf in Moore's Bay was measured from reflection times of radio-frequency pulses propagating vertically through the shelf and reflecting from the ocean, and is found to be 576± 8m. Introducing a baseline of 543 ±7m between radio transmitter and receiver allowed the computation of the basal reflection coefficient, R, separately from englacial loss. The depth-averaged attenuation length of the ice column, 〈L〉 is shown to depend linearly on frequency. The best fit (95% confidence level) is 〈L(v)〉 = (460± 20)-(180±40)vm (20 dB km-1), for the frequencies v = [0.100-0.850] GHz, assuming no reflection loss. The mean electric-field reflection coefficient is √R = 0.82 ±0.07 (1.7dB reflection loss) across [0.100-0.850] GHz, and is used to correct the attenuation length. Finally, the reflected power rotated into the orthogonal antenna polarization is

The design and performance of a fully-synchronous multi-GHz analog transientwaveform recorder I.C. ("SST") with fast and flexible trigger capabilities ispresented. The SST's objective is to provide multi-GHz sample rates withintrinsically-stable timing, Nyquist-rate sampling and high trigger bandwidth,wide dynamic range and simple operation. Containing 4 channels of 256 samplesper channel, the SST is fabricated in an inexpensive 0.25 micrometer CMOSprocess and uses a high-performance package that is 8 mm on a side. It has a1.9V input range on a 2.5V supply, exceeds 12 bits of dynamic range, and uses~128 mW while operating at 2 G-samples/s and full trigger rates. With astandard 50 Ohm input source, the SST exceeds ~1.5 GHz -3 dB bandwidth. TheSST's internal sample clocks are generated synchronously via a shift registerdriven by an external LVDS oscillator running at half the sample rate (e.g., a1 GHz oscillator yields 2 G-samples/s). Because of its purely-digitalsynchronous nature, the SST has ps-level timing uniformity that is independentof sample frequencies spanning over 6 orders of magnitude: from under 2 kHz toover 2 GHz. Only three active control lines are necessary for operation: Reset,Start/Stop and Read-Clock. When operating as common-stop device, the time ofthe stop, modulo 256 relative to the start, is read out along with the sampledsignal values. Each of the four channels integrates dual-threshold triggercircuitry with windowed coincidence features. Channels can discriminate signalswith ~1mV RMS resolution at >600 MHz bandwidth.

A monolithic solid-state linear sensor array has been designed and fabricated in a 0.35 [micro]m, 3.3 V, thin-oxide digital CMOS process. The sensor arrays are targetted at such instruments and applications as digital streak cameras, 2-D cameras for proton radiography, and fiber-optic array readout. The prototype consists of a 1-D linear array of 150 integrated photodiodes, followed by fast analog buffers and on-chip, 150-deep analog frame storage. Frame storage consists of 150 analog sample circuits per pixel, with each sample circuit including an n-channel sample switch, a 0.1 pF double-polysilicon sample capacitor, a reset switch to clear the capacitor, and a multiplexed source-follower readout buffer. Sampling speeds of 400 M-frames/s have been achieved using electrical input signals, and 100 MHz with optical input signals, both with a dynamic range of ~11.5 bits, rms. Circuit design details are presented, along with the results of electrical measurements and optical experiments with fast pulsed laser light sources at several wavelengths. A set of next-generation concept designs are also presented that aims to include PLL-based clock multiplication for 1 GHz continuous sampling, plus a new real-time trigger circuit technique that examines windowed regions of stored samples to form a sophisticated trigger decision. Index Terms--Image sensors, intelligent sensors, optical signal detection.

Direct-detection CMOS image sensors optimized for charged-particle imaging applications, such as electron microscopy and particle physics, have been designed, fabricated and characterized. Based on standard silicon CMOS Active Pixel Sensor (APS) technology, the sensor arrays uses an 8 to 20 [micro]m epitaxial layer that acts as a thicker sensitive region in the generation and collection of ionization electrons resulting from impinging high-energy particles. A range of optimizations to this technology have been developed via simulation and experimental device design. These include the simulation and measurement of charge collection efficiency versus recombination, effect of diode size and stray capacitance versus signal gain and noise, and the effect of different epitaxial silicon depths and the energy of incident electrons. Results from several experimental devices are presented and compared with simulations, including measurements from two prototypes that systematically and independently vary pixel pitch and diode area. Index Terms--Active pixel sensor, image sensors, ionization, Monte Carlo simulation, photodiodes.

Monolithic CMOS cameras for direct imaging in electron microscopy and other radiation imaging applications have been developed and have been used to capture images with high signal to noise and resolution. Based on CMOS Active Pixel Sensor (APS) technology, the arrays use an 8 to 20 [micro]m epitaxial layer that acts as a thicker sensitive region for the liberation and collection of ionization electrons resulting from impinging charged particles. This results in a 100% fill factor and a far larger signal per incident charged particle than a typical CMOS photodiode could provide. The per-pixel CDS scheme discussed in this paper has demonstrated reductions in kT/C noise by a factor of four, to 11 electrons RMS at room temperature. The CDS scheme requires only one read instead of the two reads plus pre- and post-integration subtraction required by traditional CDS, and is hence faster than alternate schemes. In addition, the test device was used in the observation of Random Telegraph Signal noise (RTS) in small-capacitance pixels under different [V.sub.gs] conditions. Index Terms--Image sensors, particle tracker, radiation detectors, smart pixels.

We describe work that extends three-dimensional (3-D) patterned overlay high-density interconnect (HDI) to high-performance imaging applications. The work was motivated by the rigorous requirements of the multiple-pulse imager for dynamic proton radiography. The optical imager has to provide large (~90%) optical fill factor, high quantum efficiency, 200-ns inter-frame time interval, and storage for >32 frames. In order to accommodate the massively parallel electronics including the signal storage for a large number of frames, it is necessary to provide novel 3-D interconnect and packaging architectures. Recently, a 3-D interconnect technology was successfully demonstrated to assemble a stack of 50 signal-processing chips into a cube. Each chip contained test connections (interconnect continuity only) simulating 160 channels of pixel read-out electronics. Test cube assemblies, based on these mock-up integrated circuits, have been fabricated to explore the feasibility of constructing functional cube arrays. A novel 3-D integrated sensor-electronics (mirror-cube) imager architecture is proposed. We also briefly review progress in the custom fast image-processing electronics. Index Terms--Adaptive lithography, die stacking, fast imagers, HDI, polymer bump bonding, 3-D interconnect.

Two CMOS image sensor circuit prototypes equipped with in situ frame storage have been fabricated and tested. Capable of 4-400 M-frames/s and between 66 and 79 dB rms dynamic range, these developments are intended for the capture of fast, brief, transient events with high resolution. Applications include accelerator-based flash radiography such as proton radiography [1]. The first is a small two-dimensional (2-D) prototype in which each pixel includes either a capacitive trans-impedance amplifier or a direct-integration source-follower front end, followed by an array of 64 frame storage sample capacitors and associated readout electronics. The acquisition of either 32 frames using correlated double sampling (CDS) at 4 M-frames/s, or 64 frames without CDS at up to 10.5 M-frames/s (-3 dB), and up to 13 b dynamic range was achieved. The second is a monolithic solid state 'streak camera,' a 1-D linear array of 150 photodiodes, with a 150-frame analog storage array. This device reached 400-M-frames/s operation with electrical test inputs, at least 100-M-frames/s operation with optical inputs, and achieves over 11 b of dynamic range. These circuits demonstrate the high performance possible with CMOS sensor circuits containing in situ frame storage. Index Terms--Active pixel sensor, CMOS, high-speed imaging, streak camera.

Active pixel sensor (APS) is a promising technology for next-generation vertex detectors. This paper discusses the design and testing of two generations of APS chips. Both are arrays of 128 by 128 pixels, each 20 by 20 [micro]m. Each array is divided into subarrays in which different sensor structures (4 in the first version and 16 in the second) and/or readout circuits are employed. Measurements of several of these structures under [Fe.sup.55] exposure are reported. The sensors have also been irradiated by 55 MeV protons to test for radiation damage. The radiation increases the noise and reduces the signal. The noise can be explained by shot noise from the increased leakage current, and the reduction in signal is due to charge being trapped in the epi layer. Nevertheless, the radiation effect is small for the expected exposures at RHIC and RHIC II. Finally, we describe our conception for mechanically supporting a thin silicon wafer in an actual detector. Index Terms--Active pixel sensor, CMOS integrated circuit, heavy ions, particle tracking, proton radiation effects, semiconductor device radiation effects, semiconductor radiation detectors, vertex detectors, X-ray image sensor.

A series of multichannel transient waveform digitization integrated circuits with up to 5 GHz sample rates and parallel 10-bit digitization have been designed, tested, and fabricated in large quantities. The current CMOS circuit uses four arrays of 128 fast switched capacitors per channel to record four parallel analog transient inputs. High-speed sample clock generation is provided by an analogically adjustable asynchronous active delay line that uses look-ahead to generate 128 multi-GHz four-way interleaved clocks without the need for external high-speed clocking. After transient capture, each channel is fed into 128 parallel 10-bit analog to digital converters for fast, channel-parallel digitization, followed by digital readout. The fast triggering and waveform capture, channel-parallel digitization and convenient word-parallel digital readout results in a responsive and low dead-time system. Acquisition sample rates range from ~ 50 kHz to ~ 3 GHz. Analog input bandwidth was measured to be ~ 350 MHz. Temporal noise is typically equivalent to ~ 1 mV root mean square (rms) for a signal-to-noise ratio of ~ 2,500 : 1 rms. Fixed-pattern spatial noise, after on-chip digitization, is equivalent to ~ 5 mV rms. Current design directions are intended improve on this technology with sample rates in excess of 10 GHz and analog bandwidth exceeding 1 GHz. Index Terms--Analog-to-digital conversion, sample and hold, switched capacitor array, transient digitizer, transient recorder.

A monolithic analog to digital converter with small silicon area and low power consumption was designed and tested for use in multichannel circuits. The chip contains a linear ramp, precision high speed comparators, pipelined counter and double buffering storage latches made in a two micron two polysilicon complementary metal-oxide-semiconductor technology. The converter is used in a dual range readout system of a scintillating calorimeter at the superconducting super collider.