88 results on '"King-Liu, Tsu-Jae"'
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2. Examining the Self-Efficacy of Community College STEM Majors: Factors Related to Four-Year Degree Attainment
3. Highly scaled (Lg ∼ 56 nm) gate-last Si tunnel field-effect transistors with ION > 100 μA/μm
4. 3D Integrated CMOS-NEM Systems: Enabling Next-Generation Computing Technology
5. Reducing adhesion energy of nano-electro-mechanical relay contacts by self-assembled Perfluoro (2,3-Dimethylbutan-2-ol) coating
6. Tuning of Schottky barrier height using oxygen-inserted (OI) layers and fluorine implantation
7. A Density Metric for Semiconductor Technology [Point of View]
8. Breakdown and Healing of Tungsten-Oxide Films on Microelectromechanical Relay Contacts.
9. Study of Germanium Epitaxial Recrystallization on Bulk-Si Substrates
10. Optimization of Flash Annealing Parameters to Achieve Ultra-Shallow Junctions for sub-45nm CMOS
11. Study of Poly-SiGe Structural Properties for Modularly Integrated MEMS
12. Mechanical Properties of Polycrystalline Silicon formed by Al-2%Si Induced Crystallization
13. Reducing adhesion energy of nano-electro-mechanical relay contacts by self-assembled Perfluoro (2,3-Dimethylbutan-2-ol) coating
14. Tilted ion implantation of spin-coated SiARC films for sub-lithographic and two-dimensional patterning
15. Changes to the Editorial Board
16. Changes to the Editorial Board
17. Tilted ion implantation as a cost-efficient sublithographic patterning technique
18. Changes to the Editorial Board
19. Electron mobility enhancement in (100) oxygen-inserted silicon channel
20. Mechanically modulated tunneling resistance in monolayer MoS2
21. 2.5 GB/s germanium gate photoMOSFET integrated to silicon photonics
22. Rapid melt grown germanium gate photoMOSFET on a silicon waveguide
23. Editorial
24. Reliability of MEM relays for zero leakage logic
25. Scaled Micro-Relay Structure with Low Strain Gradient for Reduced Operating Voltage
26. Highly scaled (Lg∼56nm) gate-last Si tunnel field-effect transistors with ION>100μA/μm
27. Steep-subthreshold-slope devices on SOI
28. Study of Random Dopant Fluctuation Effects in Germanium-Source Tunnel FETs
29. Collaborative research on emerging technologies and design
30. Mechanical Computing Redux: Relays for Integrated Circuit Applications
31. Comparative Study of FinFET Versus Quasi-Planar HTI MOSFET for Ultimate Scalability
32. Prospects for MEM logic switch technology
33. Sub-60nm Si tunnel field effect transistors with Ion >100 µA/µm
34. Tri-gate bulk CMOS technology for improved SRAM scalability
35. Seesaw Relay Logic and Memory Circuits
36. SRAM Read/Write Margin Enhancements Using FinFETs
37. Analysis of the relationship between random telegraph signal and negative bias temperature instability
38. The Effect of Random Dopant Fluctuation on Specific Contact Resistivity
39. Characterization of Nanometer-Scale Gap Formation
40. Nano-Electro-Mechanical Nonvolatile Memory (NEMory) Cell Design and Scaling
41. SRAM yield and performance enhancements with tri-gate bulk MOSFETs
42. Impact of gate line edge roughness on double-gate FinFET performance variability
43. Optimization of Flash Annealing Parameters to Achieve Ultra-Shallow Junctions for sub-45nm CMOS
44. Dual-Bit Gate-Sidewall Storage FinFET NVM and New Method of Charge Detection
45. Intrinsic Advantages of SOI Multiple-Gate MOSFET (MuGFET) for Low Power Applications
46. Characterization of Polycrystalline Silicon-Germanium Film Deposition for Modularly Integrated MEMS Applications
47. Selective Enhancement of SiO[sub 2] Etch Rate by Ar-Ion Implantation for Improved Etch Depth Control
48. ALD Refill of Nanometer-Scale Gaps with High-κ Dielectric for Advanced CMOS Technologies
49. Impact of gate line edge roughness on double-gate FinFET performance variability.
50. Optimization of Flash Annealing Parameters to Achieve Ultra-Shallow Junctions for sub-45nm CMOS.
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