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A number of reports have demonstrated the feasibility of oxide thin film transistors (TFTs) replacing silicon-based technology in active-matrix liquid-crystal displays (AMLCDs) and active-matrix organic light emitting diodes (AMOLEDs). Among oxide materials, zinc tin oxide (ZTO) is being tipped off as an appropriate alternative for amorphous-silicon. ZTO tops its adversaries because it has a robust amorphous phase compared to ZnO and has a more simple composition compared to InGaZnO. Although ZTO TFTs showed their good performance, the stability issues of these devices have not yet been addressed. Because TFTs are used in display technology, the effect of light on their electrical performance is a vital matter that should be considered. Therefore, in this work, the effect of light illumination on the negative bias temperature instability (NBTI) of ZTO TFTs is investigated.

Amorphous HfInZnO (HIZO) - thin film transistor (TFT) with the bottom gate structure were fabricated to investigate the effect of light illumination on the transfer curves and stability characteristics under negative bias stress. The TFTs with passivation layers showed promising characteristics when measured in the dark, with a saturation mobility (usat) of 9.0 cm2/Vs, a sub-threshold swing (SS) of 0.34 V/dec and an on/off ratio of ~108. However, when exposed to light of wavelengths below 500nm, the transfer curve changes remarkably, with an increase of SS and off-current (Ioff). The change in the transfer curves were also studied by examining them before and after negative bias-temperature-illumination stress. The increase of SS under light illumination can be due to the increase in the number of activated interfacial traps by photon energy.

Amorphous oxide semiconductor memory devices with HfInZnOx as the channel layer and high k dielectric stacks as the charge storage medium were fabricated. HfO2 and Al2O3 and HfAlOx films were examined as the charge trap layers. The drain current - gate voltage transfer curves of the fabricated charge trap memories show a large hysteresis due to the electron trapping and de-trapping at the interfaces between the high-k charge storage layer and the SiO2. The device structure and operational scheme for the amorphous oxide semiconductor charge trap memories were suggested based on these properties.

Interfacial barrier layers (IBLs), such as a thermally grown using , thermally nitrided using , and an atomic layer deposited (ALD) layer, were used as an interface layer between a sputtered film and a Si substrate. Sr-silicate phase formation at the interface between the film and Si substrate was suppressed by these IBLs. The ALD layer was the most effective diffusion/reaction barrier against Si diffusion and the interfacial reactions among the IBLs examined. However, the crystallinity of the layer deteriorated as a result of a chemical reaction with the underlying ALD layer, which decreased the permittivity of the layer. The film with a IBL showed lower Si diffusion and better crystallinity, which provided the optimum dielectric properties of the film.

This study examined the positive bias temperature instability (PBTI) of n-type metal-oxide-semiconductor field effect transistor (nMOSFET) characteristics and the negative bias temperature instability (NBTI) of p-type metal-oxide-semiconductor field effect transistor (pMOSFET) characteristics of gate dielectrics with a metal gate. The interface trap charge and bulk oxide trap charge densities were separately estimated to determine the defects responsible for the threshold voltage shift during the BTI stress. The contribution of to the shift for nMOSFET PBTI and pMOSFET NBTI was and , respectively. In addition, the estimated activation energy of and was 0.10 and 0.03 eV, respectively, for nMOSFET PBTI, and 0.11 and 0.17 eV, respectively, for pMOSFET NBTI. It was confirmed that the main degradation mechanism of nMOSFET PBTI is related to the generation of oxide trap charges. However, the degradation under pMOSFET NBTI stress is due to the generation of both interface states and oxide trap charges. By measuring the stress and recovery characteristics under various bias conditions, it was also found that the electron trapping/detrapping characteristics are dominant in the nMOSFET, whereas the generation of both hole trapping/detrapping and interface states competitively occurs in the pMOSFET.

Abnormal hysteresis was found to exist in amorphous Hf-In-Zn-O thin film transistors under illumination. Unlike common hysteresis, a disparity in the sub-threshold swing of the transfer curves was observed. This distinction showed a linear increase according to light intensity, and is thought to come from the light enabled motion of ionized oxygen vacancies (VO 2+). The positively charged nature of these defects causes them to show a different distribution in the channel according to sweep direction. The hysteresis decreased when the sweep range was decreased, and vanished when the sweep range fell in the positive region only.

Hole current was directly observed in oxide semiconductors under illumination. Two stacks were fabricated, with In-Ga-Zn-O (IGZO) as the channel and SiO2 or SiNx as the gate insulator. X-ray photoelectron spectroscopy confirmed the IGZO/SiNx interface has no hole barrier while the IGZO/SiO2 interface has a significant one. This was used to analyze hole generation in IGZO by illuminating light at various wavelengths. As a result, a threshold wavelength, where holes start to emerge in the channel, was found to exist. Negative bias-illumination-temperature stress experiments showed that no additional threshold voltage shift exists at wavelengths longer than this threshold wavelength.

Interfacial barrier layers (IBLs), such as a thermally grown SiO2using O3, thermally nitrided SiOxNyusing NH3, and an atomic layer deposited (ALD) HfO2layer, were used as an interface layer between a sputtered SrTiO3film and a Si substrate. Sr-silicate phase formation at the interface between the SrTiO3film and Si substrate was suppressed by these IBLs. The ALD HfO2layer was the most effective diffusion/reaction barrier against Si diffusion and the interfacial reactions among the IBLs examined. However, the crystallinity of the SrTiO3layer deteriorated as a result of a chemical reaction with the underlying ALD HfO2layer, which decreased the permittivity of the SrTiO3layer. The SrTiO3film with a SiOxNyIBL showed lower Si diffusion and better crystallinity, which provided the optimum dielectric properties of the film.

Amorphous HfInZnO (HIZO) - thin film transistor (TFT) with the bottom gate structure were fabricated to investigate the effect of light illumination on the transfer curves and stability characteristics under negative bias stress. The TFTs with passivation layers showed promising characteristics when measured in the dark, with a saturation mobility (µsat) of 9.0 cm2/Vs, a sub-threshold swing (SS) of 0.34 V/dec and an on/off ratio of ~108. However, when exposed to light of wavelengths below 500nm, the transfer curve changes remarkably, with an increase of SS and off-current (Ioff). The change in the transfer curves were also studied by examining them before and after negative bias-temperature-illumination stress. The increase of SS under light illumination can be due to the increase in the number of activated interfacial traps by photon energy.

This study examined the positive bias temperature instability (PBTI) of n-type metal-oxide-semiconductor field effect transistor (nMOSFET) characteristics and the negative bias temperature instability (NBTI) of p-type metal-oxide-semiconductor field effect transistor (pMOSFET) characteristics of HfO2gate dielectrics with a metal gate. The interface trap charge (ΔNit)and bulk oxide trap charge (ΔNot)densities were separately estimated to determine the defects responsible for the threshold voltage (Vth)shift during the BTI stress. The contribution of ΔNitto the Vthshift for nMOSFET PBTI and pMOSFET NBTI was ∼5and ∼30%, respectively. In addition, the estimated activation energy (Ea)of ΔNitand ΔNotwas 0.10 and 0.03 eV, respectively, for nMOSFET PBTI, and 0.11 and 0.17 eV, respectively, for pMOSFET NBTI. It was confirmed that the main degradation mechanism of nMOSFET PBTI is related to the generation of oxide trap charges. However, the degradation under pMOSFET NBTI stress is due to the generation of both interface states and oxide trap charges. By measuring the stress and recovery characteristics under various bias conditions, it was also found that the electron trapping/detrapping characteristics are dominant in the nMOSFET, whereas the generation of both hole trapping/detrapping and interface states competitively occurs in the pMOSFET.