32 results on '"Kim, Hoonki"'
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2. 3nm Gate-All-Around (GAA) Design-Technology Co-Optimization (DTCO) for succeeding PPA by Technology
3. A 3-nm Gate-All-Around SRAM Featuring an Adaptive Dual-Bitline and an Adaptive Cell-Power Assist Circuit
4. Synthesis method based on genetic algorithm for designing EDFA gain flattening LPFGs having phase-shifted effect
5. 24.3 A 3nm Gate-All-Around SRAM Featuring an Adaptive Dual-BL and an Adaptive Cell-Power Assist Circuit
6. A Wide-Range Static Current-Free Current Mirror-Based LS With Logic Error Detection for Near-Threshold Operation
7. An Embedded Level-Shifting Dual-Rail SRAM for High-Speed and Low-Power Cache
8. Bitline Charge-Recycling SRAM Write Assist Circuitry for$V_{\mathrm{MIN}}$Improvement and Energy Saving
9. Smart scaling technology for advanced FinFET node
10. Half-and-Half Compare Content Addressable Memory with Charge-Sharing Based Selective Match-Line Precharge Scheme
11. A 7nm FinFET SRAM using EUV lithography with dual write-driver-assist circuitry for low-voltage applications
12. An ultra-dense irradiation test structure with a NAND/NOR readout chain for characterizing soft error rates of 14nm combinational logic circuits
13. Statistical characterization of radiation-induced pulse waveforms and flip-flop soft errors in 14nm tri-gate CMOS using a back-sampling chain (BSC) technique
14. 12.2 A 7nm FinFET SRAM macro using EUV lithography for peripheral repair analysis
15. A 10 nm FinFET 128 Mb SRAM With Assist Adjustment System for Power, Performance, and Area Optimization
16. Bitline Charge-Recycling SRAM Write Assist Circuitry for $V_{\mathrm{MIN}}$ Improvement and Energy Saving.
17. A 0.4-mW, 4.7-ps Resolution Single-Loop TDC Using a Half-Delay Time Integrator
18. An 8bit, 2.6ps two-step TDC in 65nm CMOS employing a switched ring-oscillator based time amplifier
19. Circuit techniques for mitigating short-term vth instability issues in successive approximation register (SAR) ADCs
20. An 8-bit Analog-to-Digital Converter based on the voltage-dependent switching probability of a Magnetic Tunnel Junction
21. Digital calibration technique using a signed counter for charge pump mismatch in phase‐locked loops
22. A WIDEBAND CMOS CASCADED VARIABLE GAIN AMPLIFIER USING UNEQUALLY DISTRIBUTED GAIN CONTROL FOR DVB-S.2 RECEIVER
23. Power transfer characteristics of four-coil magnetic resonance system according to the position of self-resonant coils
24. A 1-mW Solar-Energy-Harvesting Circuit Using an Adaptive MPPT With a SAR and a Counter
25. An Energy-Efficient Fast Maximum Power Point Tracking Circuit in an 800-μW Photovoltaic Energy Harvester
26. A 0.4-mW, 4.7-ps Resolution Single-Loop $\Delta \Sigma $ TDC Using a Half-Delay Time Integrator.
27. A 6MHz CMOS reference clock generator with temperature and supply voltage compensation
28. An Energy Efficient $V_{\rm PP}$ Generator With Fast Ramp-Up Time for Mobile DRAM
29. A low power consumption 10-bit rail-to-rail SAR ADC using a C-2C capacitor array
30. Synthesis of Flat-Top Bandpass Filters Using Two-Band Rejection Long-Period Fiber Gratings
31. Analysis of Concatenated Long Period Fiber Gratings Having Phase-Shifted and Cascaded Effects
32. An Energy Efficient VPP Generator With Fast Ramp-Up Time for Mobile DRAM.
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