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Neuromorphic computing systems are biologically inspired approaches created from many highly connected neurons to model neuroscience theories and solve machine learning problems. They promise to drastically improve the efficiency of critical computational tasks such as decision-making and perception. Combining neuromorphic computing systems and 3D interconnect (3D-NoC) technology leads to an advanced architecture that inherits the benefits of both computing and interconnect paradigms. However, designing large-scale neuromorphic systems based on 3D-NoC faces several challenges, including thermal power, power distribution, increased power density at the heat sink interface, and fabrication requirements. This work tackles the thermal issues in designing large-scale neuromorphic systems by proposing a Balanced Thermal-State-Aware Mapping (BTSAM) for 3D-NoC-based neuromorphic systems. This includes a Periodic Activity Scoring (PAS), a Seesaw Neuron Clustering (SNC) method, and a thermal-aware genetic algorithm to eliminate hotspots, balance the thermal state, and lower the temperature while keeping the system’s accuracy acceptable. Evaluation results on various system configurations demonstrate a notable up to 12.4 K and 5.2 K temperature reduction compared to linear methods and HeterGenMap, respectively, and a $4\times $ increase in Mean-Time-to-Failure (MTTF), with an acceptable power and area overheads and little degradation of the communication cost.

While task mapping for multi-core systems is known as an NP-hard problem, mapping for neuromorphic systems even scale it up due to a high number of neurons per core and a high number of core per system. Moreover, mapping for neuromorphic systems also has several challenges such as heterogeneous computing core or communication fabrics, and potential defects in neurons or routing units. Therefore, this paper presents a genetic algorithm framework named HeterGenMap which is a Genetic Algorithm framework for mapping multiple-layer Spiking Neural Network systems to solve the aforementioned problems. The results show that HeterGenMap improves the overall communication cost by 11.04-26.77% in comparison to the linear mapping. Moreover, under link faulty scenarios, neuron defects, or multi-chip designs, HeterGenMap can reduce the communication cost by 3.41-31.34%, 7.01%-41.51%, and 34.21-45.56% in comparison to the linear approach, respectively. The validation in hardware also demonstrated that HeterGenMap reduces the inference time by 63.10-77.87% from the linear mapping.

Neuromorphic computing utilizes spiking neural networks (SNNs) to offer power/energy-efficient solutions for complex machine-learning problems in hardware. However, neural circuits are prone to faults caused by variability in the manufacturing flow, process variations, and manufacturing defects. This work proposes a mapping approach, R-MaS3N, that leverages the reuse of existing neurons for robust mapping of SNNs to a 3D-NoC-based neuromorphic system (NR-NASH). A heuristic-based partitioning technique is employed to partition neurons in the layers of an SNN application using neuron firing patterns. Moreover, a neuronal partitioning approach cluster mapped neurons in the layers of the neuromorphic neural circuits based on connectivity patterns and spiking activities. Evaluation results show that the proposed fault-tolerant mapping method maintains a remapping efficiency of 100% with a fault rate of 40% in the 3D NoC-based neuromorphic system. With a NoC system configuration of $4\times 4\times 4$ and 256 neurons per cluster, our approach has a remapping time of $71\times $ less than the previous approach with the same NoC system configuration parameters. In addition, the mean time to failure (MTTF) of the mapping method for system configuration $5\times 5\times 5$ NoC size at a 40% fault rate surpasses the previous method at 20% fault rate by 16% for $4\times 4\times 4$ NoC size.

Spiking Neural Networks (SNNs) show their potential for lightweight low-power inferences because they mimic the functionality of the biological brain. However, one of the major challenges of SNNs like other neural networks is memory-wall and power-wall when accessing data (synaptic weights) from memory. It limits the potential of spiking neural networks implemented on edge devices. In this paper, we present a novel spiking computing hardware architecture named NASH-3DM using 3D-IC-based stacking memory with power supply awareness to effectively decrease power consumption for AI-enabled edge devices. Instead of storing one or multiple weights in a single memory word, we split them into small subsets and allocate each subset into a separate memory in every stacking layer. With the natural separation of stack layers, our system can activate and deactivate each layer separately. Therefore, it can offer in-situ (online, post-manufacture, and without interruption) dynamic quantization with multiple operating modes. With the CMOS 45nm technology, our energy per synaptic operation for MNIST classification can reduce by 36.67% while having 0.93%-1.14% accuracy loss at 5-bit quantization. The energy per synaptic operation reduction for the CIFAR10 dataset is 36.68% when switching from the 16-bit active operation to the in-situ 10-bit one with an accuracy loss of 5.69%.

Neuromorphic computing uses spiking neuron network models to solve machine learning problems in a more energy-efficient way when compared to conventional artificial neural networks. However, mapping the various network components to the neuromorphic hardware is not trivial to realize the desired model for an actual simulation. Moreover, neurons and synapses could be affected by noise due to external interference or random actions of other components (i.e., neurons), which eventually lead to unreliable results. This work proposes a fault-tolerant spiking neural network mapping algorithm and architecture to a 3D network-on-chip (NoC)-based neuromorphic system (R-NASH-II) based on a rank and selection mapping mechanism (RSM). The RSM allows the ranking and rapid selection of neurons for fault-tolerant mapping. Evaluation results show that with our proposed mechanism, we could maintain a mapping efficiency of 100% with 20% spare rate and a fault rate (40%) more than in the previous mapping framework. The Monte Carlo simulation evaluation of reliability shows that the RSM mechanism has increased the mean time to failure (MTTF) of the previous mapping technique by 43% on average. Furthermore, the operational availability of the RSM for mapping to a $4\times 4\times 4$ (smallest) and $6\times 6\times 6$ (largest) NoC is 88% and 67% respectively.

Neuromorphic systems have shown improvements over the years, leveraging Spiking neural networks (SNN) event-driven nature to demonstrate low power consumption. As neuromorphic systems require high integration to form a functional silicon brain-like, moving to 3D integrated circuits (3D-ICs) with three-dimensional network on chip (3D-NoC) interconnect is a suitable approach that allows scalable design, shorter connections, and lower power consumption. However, highly dense neuromorphic systems also encounter the reliability issue where a single point of failure can affect the systems’operation. Because neuromorphic systems rely heavily on spike communication, an interruption or violation in the timing of spike communication can adversely affect the performance and accuracy of a neuromorphic system. This paper presents NASH,a a fault-tolerant 3D-NoC based neuromorphic system that incorporates as processing elements, lightweight spiking neuron processing cores (SNPCs) with spike-timing-dependent-plasticity (STDP) on-chip learning. Each SNPC houses 256 leaky integrate-and-fire (LIF) neurons and 65k synapses. Evaluation results on MNIST classification, using the fault-tolerant shortest-path K-means-based multicast routing algorithm (FTSP-KMCR), show that the NASH system can maintain high accuracy for up to 30% permanent fault in the interconnect with an acceptable area and power overheads when compared to other existing systems.aThis project is supported by the University of Aizu, Competitive Research Funding (CRF), Ref. UoA-P6-2020

As one of the most promising technologies to realize 3D Integrated Circuits (3D-ICs), Through-Silicon-Via (TSV) acts as the inter-layer link inside 3D Networks-on-Chip. However, the reliability issues due to the low yield rates and the sensitivity to thermal hotspots and stress issues are preventing TSV-based 3D-ICs from being widely and efficiently used. To ensure the correctness of TSV connections at run-time, detecting multiple (clustering) defects is an important feature. While Error Correction Codes are limited by a certain number of detectable faults, using Built-In-Self-Test (BIST) prevents the system from operating normally during the test time. This paper first presents a Parity Product Code (PPC) with the ability to correct one fault and detect, at least, two faults. Second, we present extended PPC (EPPC) to detect multiple defects within the links of Networks-on-Chip by using two or more additional matrices. Furthermore, we present the distance-aware version of EPPC to detect multiple defects by using only one extra matrix. The results show that the distance-aware EPPC can detect 100% of clustering defects and multiple random defects within two and three cycles, respectively. The performance evaluation for Network-on-Chip testing also shows no degradation while providing an extremely short response time (2-3 cycles).

Through-Silicon-Via (TSV) based 3D Integrated Circuits (3D-IC) are one of the most advanced architectures by providing low power consumption, shorter wire length and smaller footprint. However, 3D-ICs confront lifetime reliability due to high operating temperature and interconnect reliability, especially the Through-Silicon-Via (TSV), which can significantly affect the accuracy of the applications. In this paper, we present an online method that supports the detection and correction of lifetime TSV failures, named IaSiG. By reusing the conventional recovery method and analyzing the output syndromes, IaSiG can determine and correct the defective TSVs. Results show that within a group, R redundant TSVs can fully localize and correct R defects and support the detection of R+1 defects. Moreover, by using G groups, it can localize up to GxR and detect up to G x (R + 1) defects. An implementation of IaSiG for 32-bit data in eight groups and two redundancies has a worst-case execution time (WCET) of 5,152 cycles while supporting at most 16 defective TSVs (50% localization). By integrating IaSiG onto a 3D Network-on-Chip, we also perform a grid-search based empirical method to insert suitable numbers of redundancies into TSV groups. The empirical method takes the operating temperature as the factor of accelerated fault due to the fact that temperature is one of the major issues of 3D-ICs. The results show that the proposed method can reduce the number of redundancies from the uniform method while still maintaining the required Mean Time to Failure.

Spiking Neuromorphic systems have been introduced as promising platforms for energy-efficient spiking neural network (SNNs) execution. SNNs incorporate neuronal and synaptic states in addition to the variant time scale into their computational model. Since each neuron in these networks is connected to many others, high bandwidth is required. Moreover, since the spike times are used to encode information in SNN, a precise communication latency is also needed, although SNN is tolerant to the spike delay variation in some limits when it is seen as a whole. The two-dimensional packet-switched network-on-chip was proposed as a solution to provide a scalable interconnect fabric in large-scale spike-based neural networks. The 3D-ICs have also attracted a lot of attention as a potential solution to resolve the interconnect bottleneck. Combining these two emerging technologies provides a new horizon for IC design to satisfy the high requirements of low power and small footprint in emerging AI applications. Moreover, although fault-tolerance is a natural feature of biological systems, integrating many computation and memory units into neuromorphic chips confronts the reliability issue, where a defective part can affect the overall system's performance. This paper presents the design and simulation of R-NASH-a reliable three-dimensional digital neuromorphic system geared explicitly toward the 3D-ICs biological brain's three-dimensional structure, where information in the network is represented by sparse patterns of spike timing and learning is based on the local spike-timing-dependent-plasticity rule. Our platform enables high integration density and small spike delay of spiking networks and features a scalable design. R-NASH is a design based on the Through-Silicon-Via technology, facilitating spiking neural network implementation on clustered neurons based on Network-on-Chip. We provide a memory interface with the host CPU, allowing for online training and inference of spiking neural networks. Moreover, R-NASH supports fault recovery with graceful performance degradation.