1. Nano-imprint lithography: Templates, imprinting and wafer pattern transfer
- Author
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Ngoc V. Le, William J. Dauksher, Pawitter J. S. Mangat, Jeffrey H. Baker, K. Gehoski, Kevin J. Nordquist, Diana Convey, S. R. Young, and Eric S. Ainley
- Subjects
Fabrication ,Computer science ,Process (engineering) ,Nanotechnology ,Hardware_PERFORMANCEANDRELIABILITY ,Condensed Matter Physics ,Atomic and Molecular Physics, and Optics ,Surfaces, Coatings and Films ,Electronic, Optical and Magnetic Materials ,International Technology Roadmap for Semiconductors ,Template ,Nanolithography ,Hardware_INTEGRATEDCIRCUITS ,Wafer ,Electrical and Electronic Engineering ,Lithography ,Imprinting (organizational theory) - Abstract
Nano-imprint lithography is attracting attention as a low cost method for printing nanometer-scale geometries and has obtained placement on the International Technology Roadmap for Semiconductors as a potential lithography solution at the 32 and 22nm fabrication nodes [International Technology Roadmap for Semiconductors, 2003 ed.]. As a result, nano-imprint technology and infrastructure development related to template infrastructure, imprinting capabilities, and wafer-level pattern transfer processes are essential to successfully make the transition from research and development to a viable manufacturing processing technique suitable for multiple applications. Motorola Labs has been focusing on developing the template and wafer-level processes while optimizing the imprinting process and collaborating with external partners to optimize both the inspection and repair of imprint templates. This paper reviews recent results of the above-mentioned focus areas.
- Published
- 2006