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Herein, we present a design analysis and optimization of open-cladded plasmonic waveguides on a Si3N4 photonic waveguide platform targeting CMOS-compatible manufacturing. For this purpose, two design approaches have been followed aiming to efficiently transfer light from the hosting photonic platform to the plasmonic waveguide and vice versa: (i) an in-plane, end-fire coupling configuration based on a thin-film plasmonic structure and (ii) an out-of-plane directional coupling scheme based on a hybrid slot waveguide. A comprehensive numerical study has been conducted, initially deploying gold as the reference metal material for validating the numerical models with already published experimental results, and then aluminum and copper have been investigated for CMOS manufacturing revealing similar performance. To further enhance coupling efficiency from the photonic to the plasmonic part, implementation of plasmonic tapering schemes was examined. After thorough investigation, plasmo-photonic structures with coupling losses per single interface in the order of 1 dB or even in the sub-dB level are proposed, which additionally exhibit increased tolerance to deviations of critical geometrical parameters and enable CMOS-compatible manufacturing. [ABSTRACT FROM AUTHOR]

In this paper we present a thorough simulation-based analysis for the design of multi-step couplers bridging seamlessly plasmonic barium titanate oxide (BTO) ferroelectric phase shifters and thick silicon nitride (Si 3 N 4 ) waveguides for the O-band. The targeted plasmonic waveguides are a hybrid plasmonic waveguide (HPW) providing low propagation losses and a plasmonic metal-insulator-metal (MIM) slot waveguide offering a high confinement factor for high modulation efficiency. The proposed plasmonic platforms are formed by Copper (Cu) providing CMOS compatibility. The analysis is based on 2D-FD eigenvalue and 3D-FDTD numerical simulations targeting to identify the optimum geometries ensuring the lowest coupling losses, calculated as 1.75dB for the HPW geometry and 1.29dB for the MIM configuration. The corresponding confinement factors are 31.39% and 56.2% for the HPW and MIM waveguides, respectively.

In this paper, we present a systematic analysis for the design of Si-rich-nitride (SRN) based interposer waveguide layers interfacing InP-based devices and Si 3 N 4 waveguides, towards monolithic co-integration of active and passive elements through a Back-End-Of-Line process. The investigation is performed via extensive 2D-eigenvalue and 3D-FDTD electromagnetic simulations and focuses on three different interposer designs, where performance in terms of coupling loss and back reflections is exchanged for fabrication complexity. In addition, a tolerance analysis is performed for the demonstration of the proposed coupling scheme's resilience to fabrication misalignments. The calculations use for the refractive index of the SRN interposer, real values extracted from ellipsometry measurements of a novel ultra-Si-rich-nitride material developed and engineered for this purpose. This new material provides tunability in the real part of the refractive index with low-stress crack free samples grown up to 500nm thickness. Test structures with cutbacks featuring waveguides of 500 × 500nm 2 cross section formed via e-beam lithography reveal 15dB/cm propagation losses in line with similar amorphous silicon-rich nitride (aSi:N) materials. The proposed coupling concept although assumes an InP active medium, can be applied also with GaAs based lasers and dual facet devices such as Semiconductor Optical Amplifiers (SOAs) and electroabsorption modulators. In addition, all proposed designs are compatible in terms of critical dimensions with low cost 248nm DUV lithography targeting to maximize the low-cost advantage of the Si 3 N 4 platform with very high coupling performance. Our results are expected to pave the way for the generation of a versatile, low cost, high performance monolithic InP-Quantum-Dot (QD)/Si 3 N 4 platform on a common Si substrate.

Co-integrating CMOS plasmonics and photonics became the "sweet spot" to hit in order to combine their benefits and allow for volume manufacturing of plasmo-photonic integrated circuits. Plasmonics can naturally interface photonics with electronics while offering strong mode confinement, enabling in this way on-chip data interconnects when tailored to single-mode waveguides, as well as high-sensitivity biosensors when exposing Surface-Plasmon-Polariton (SPP) modes in aqueous environment. Their synergy with low-loss photonics can tolerate the high plasmonic propagation losses in interconnect applications, offering at the same time a powerful portfolio of passive photonic functions towards avoiding the use of bulk optics for SPP excitation and facilitating compact biosensor setups. The co-integration roadmap has to proceed, however, over the utilization of fully CMOS compatible material platforms and manufacturing processes in order to allow for a practical deployment route. Herein, we demonstrate for the first time Aluminum plasmonic waveguides co-integrated with Si 3 N 4 photonics using CMOS manufacturing processes. We validate the data carrying credentials of CMOS plasmonics with 25 Gb/s data traffic and we confirm successful plasmonic propagation in both air and water-cladded waveguide configurations. This platform can potentially fuel the deployment of co-integrated plasmonic and photonic structures using CMOS processes for biosensing and on-chip interconnect applications.