Search

Your search keyword '"Kenichi Takamiya"' showing total 7 results
Start Over Author "Kenichi Takamiya"
7 results on '"Kenichi Takamiya"'

1. Design and Performance of a 1 ms High-Speed Vision Chip with 3D-Stacked 140 GOPS Column-Parallel PEs †

Author

Atsushi Nose, Tomohiro Yamazaki, Hironobu Katayama, Shuji Uehara, Masatsugu Kobayashi, Sayaka Shida, Masaki Odahara, Kenichi Takamiya, Shizunori Matsumoto, Leo Miyashita, Yoshihiro Watanabe, Takashi Izawa, Yoshinori Muramatsu, Yoshikazu Nitta, and Masatoshi Ishikawa

Subjects
vision chip, high-speed image sensor, detection, tracking, Chemical technology, TP1-1185
Abstract

We have developed a high-speed vision chip using 3D stacking technology to address the increasing demand for high-speed vision chips in diverse applications. The chip comprises a 1/3.2-inch, 1.27 Mpixel, 500 fps (0.31 Mpixel, 1000 fps, 2 × 2 binning) vision chip with 3D-stacked column-parallel Analog-to-Digital Converters (ADCs) and 140 Giga Operation per Second (GOPS) programmable Single Instruction Multiple Data (SIMD) column-parallel PEs for new sensing applications. The 3D-stacked structure and column parallel processing architecture achieve high sensitivity, high resolution, and high-accuracy object positioning.

Published
2018
Full Text
View/download PDF

5. Design and Performance of a 1 ms High-Speed Vision Chip with 3D-Stacked 140 GOPS Column-Parallel PEs †

Author

Hironobu Katayama, Shuji Uehara, Tomohiro Yamazaki, Yoshinori Muramatsu, Shizunori Matsumoto, Yoshihiro Watanabe, Masaki Odahara, Masatoshi Ishikawa, Atsushi Nose, Leo Miyashita, Yoshikazu Nitta, Sayaka Shida, Kenichi Takamiya, Takashi Izawa, and Masatsugu Kobayashi

Subjects
Computer science, detection, vision chip, 02 engineering and technology, lcsh:Chemical technology, Biochemistry, Column (database), Article, Analytical Chemistry, Giga, 0202 electrical engineering, electronic engineering, information engineering, Vision chip, lcsh:TP1-1185, SIMD, Electrical and Electronic Engineering, Instrumentation, business.industry, 020208 electrical & electronic engineering, 020207 software engineering, tracking, Chip, Atomic and Molecular Physics, and Optics, high-speed image sensor, business, Sensitivity (electronics), Computer hardware
Abstract

We have developed a high-speed vision chip using 3D stacking technology to address the increasing demand for high-speed vision chips in diverse applications. The chip comprises a 1/3.2-inch, 1.27 Mpixel, 500 fps (0.31 Mpixel, 1000 fps, 2 × 2 binning) vision chip with 3D-stacked column-parallel Analog-to-Digital Converters (ADCs) and 140 Giga Operation per Second (GOPS) programmable Single Instruction Multiple Data (SIMD) column-parallel PEs for new sensing applications. The 3D-stacked structure and column parallel processing architecture achieve high sensitivity, high resolution, and high-accuracy object positioning.

Published
2018

6. 4.9 A 1ms high-speed vision chip with 3D-stacked 140GOPS column-parallel PEs for spatio-temporal image processing

Author

Yoshihiro Watanabe, Hironobu Katayama, Sayaka Shida, Shuji Uehara, Yoshinori Muramatsu, Leo Miyashita, Takashi Izawa, Masaki Odahara, Masatsugu Kobayashi, Shizunori Matsumoto, Yasuaki Hisamatsu, Tomohiro Yamazaki, Atsushi Nose, Kenichi Takamiya, and Masatoshi Ishikawa

Subjects
0209 industrial biotechnology, Signal processing, Machine vision, Computer science, business.industry, 010401 analytical chemistry, Image processing, 02 engineering and technology, Chip, 01 natural sciences, Column (database), Object detection, 0104 chemical sciences, Computational science, Reduction (complexity), 020901 industrial engineering & automation, Computer vision, Artificial intelligence, business
Abstract

High-speed vision systems that combine high-frame-rate imaging and highly parallel signal processing enable instantaneous visual feedback to rapidly control machines over human-visual-recognition speeds. Such systems also enable a reduction in circuit scale by using a fast and simple algorithm optimized for high-frame-rate processing [1]. Previous studies on vision systems and chips [1–4] have yielded low imaging performance due to large matrix-based processing element (PE) parallelization [1–3], and low functionality of the limited-purpose column-parallel PE architecture [4], constraining vision-chip applications.

Published
2017

7. A 17.7Mpixel 120fps CMOS image sensor with 34.8Gb/s readout

Author

Hirotaka Murakami, Toshihiro Furusawa, Koji Mishina, Yoshinori Muramatsu, Hiroyuki Iwaki, Hiroshi Shiroshita, Yuji Gendai, Tatsuya Ichikawa, Kenichi Takamiya, Hiroyuki Tsuchiya, and Takayuki Toyama

Subjects
Physics, Pixel, Interference (communication), CMOS, Image quality, Dynamic range, ComputingMethodologies_IMAGEPROCESSINGANDCOMPUTERVISION, Electronic engineering, Image sensor, Image resolution, Data transmission
Abstract

Recently, the demands to achieve both high-speed and high-quality imaging — including high A/D resolution — have increased. The new target specification is 60fps Ultra-High-Definition with 12b resolution. This imaging requires 24Gb/s, while reported CMOS image sensors have reached up to 6.5Gb/s [1–4]. This paper presents a 34.8Gb/s CMOS image sensor with high image quality, which realizes 17.7M pixels at 120fps with 12b resolution and a dynamic range of over 75dB (one of the highest image qualities, compared with data from [2]). Generally there exists a trade-off between high-speed imaging and high image quality. This is because high-speed imaging brings high power with high thermal noise, which also degrades the signal quality, and because fast data transfer may require more output pins, bringing more interference.

Published
2011

Catalog

Books, media, physical & digital resources
See catalog results