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This article presents a distributed analysis of 2-D plate capacitors with resistive top and bottom plates, which results in two coupled partial differential equations in two variables. The exact solutions for the input impedance of a rectangular capacitor are derived for several contacting scenarios. Using frequency power series analysis, we prove the resistance decoupling theorem: the effective (low frequency) series resistance of a plate capacitor is the sum of the effective resistances of the top and bottom plates considered separately. The exact effective resistance can be calculated by assuming a uniform vertical capacitive current flow between the two plates. Based on this theorem, the effective resistance for any contact scenario is derived. Our analysis also results in a geometry-dependent model for the intrinsic base resistance of BJTs that is more accurate than any previous model.

This article presents a simple method to create corner models to capture process variations for the lookup table-based MOSFET models through inputs and outputs mapping. The electrical specifications, including the threshold voltage, peak transconductance, ON-state resistance, saturation current, and gate oxide thickness, can be fitted through five model parameters. The effectiveness of the method is demonstrated by both the FinFET model BSIM-CMG and the planar MOSFET measurement data.

For structurally symmetric field-effect transistors with respect to the source and the drain, their models should be electrically symmetric about the source–drain interchange. This article shows that the commonly used drain–source voltage clamping technique breaks such a symmetry. This article then presents a symmetric source and drain voltage clamping scheme to solve the problem. The effectiveness of the new scheme is demonstrated by both the planar MOSFET model PSP and the FinFET model BSIM-CMG.

Smoothly clamping the drain–source voltage to its saturated value is a common technique used in compact modeling of transistors, such as MOSFETs, JFETs, and HEMTs. The most widely used approach, based on the power function, is not ${C}^{\infty }$ . This article proposes general formulas to construct ${C}^{\infty }$ clamping functions. Specifically, a new square root form is proposed, which is better than the existing methods and other forms in terms of derivatives and computational efficiency. The new clamping function is verified in the PSP model. It improves both the Gummel symmetry and the harmonic balance simulation.

This Special Issue is dedicated to recent research in the field of compact modeling of semiconductor devices. This is the first J-EDS Special Issue on compact modeling. In the last years, a number of new semiconductor device structures, for electronic and photonic applications, have been developed. Compact models are needed for the incorporation of these new devices in integrated circuits. Therefore, a Special Issue was needed to present recent compact modeling solutions for semiconductor devices

This paper details a robust parameter extraction flow for the PSPHV LDMOS transistor model. The procedure uses a global scaling parameter set and accounts for self-heating. We describe how to determine parameters associated with important physical effects specific to PSPHV: non-uniform lateral channel doping; the Kirk effect; internal drain voltage clamping; and the drain expansion effect. The method is verified on devices from different technologies. Verilog-A code for PSPHV is publicly available.

This article presents PSPHV, a surface-potential-based compact model for laterally diffused MOS (LDMOS) transistors. PSPHV includes a new drain voltage scaling technique that enables accurate modeling of saturation in transistors with nonuniform lateral doping; gate bias-dependent interface charge, which models the gradual channel turn- ON seen in devices with halo doping; internal drain bias clamping, which eliminates the capacitance spikes seen in most existing LDMOS models; and a new avalanche current model for the drift region that accounts for the Kirk effect. PSPHV models the drain expansion effect and diode reverse recovery and is verified against experimental data.

This paper generalizes a smoothing method for globally continuous piecewise functions based on limiting functions, with and without considering symmetry. The resulting function is infinitely differentiable. The method uses an upper limiting function, a lower limiting function, and a both-side limiting function. Three forms of the upper limiting functions are reviewed, namely square root, power, and log–exp. A general method of constructing the lower and both-side limiting functions from the upper limiting function is developed. All missing limiting functions in the three forms are derived, and the set is complete. The monotonicity of the limiting functions is proved. The usage in device compact modeling is demonstrated. In general, this method is better than the window-function-based method.

This Special Issue is dedicated to recent research in the field of compact modeling for circuit design. The topics included all device structures, provided it was demonstrated that the presented compact modeling solutions were implementable in circuit design tools. The last Special Issue addressing compact modeling of all types of semiconductor devices was published in 2006. Since then, new device structures, and with different materials, have emerged, and significant and successful research in compact advance device modeling has been done, as well in the application of compact models to circuit design. Therefore, a new Special Issue was needed that could include high-quality papers in these topics.

This paper examines the impact of dummy gates on layout dependent effects (LDE) modeling of multi-finger MOSFETs. The LDE of the multi-finger MOSFETs without dummy gates is first measured and modeled, on top of that, a formula to calculate the LDE of each gate is derived based on linear decomposition. Then a general formula to model the LDE of devices with arbitrary number of dummy gates is derived. The formulas can be used in current mirror designs to determine the number of dummy gates needed for good matching as well as to model the LDEs for devices sharing the same active region. The formulas have been verified by measurement data of MOSFETs with either unpaired or paired gates.

This paper presents the details of JFETIDG, a compact model for independent dual-gate junction field-effect transistors with any combination of p-n junction or MOS gates. JFETIDG accounts for nonlinearity from depletion pinching, velocity saturation, and self-heating, and includes extensive modeling of geometry and temperature dependences, parasitics, noise, and statistical variations. We also demonstrate that it accurately models long channel junctionless MOS transistors. The model is verified by comparison with TCAD simulations and experimental data. Verilog-A code for JFETIDG is available in the public domain.

This paper presents an improved modeling method for LDMOS with non-uniform lateral channel doping in three aspects: more accurate DC modeling from a new Vds scaling technique that accounts for the difference in threshold voltage between the source and the drain from non-uniform lateral doping; elimination of spikes in capacitances by clamping the internal drain voltage when the drift region is depleted; and a new avalanche current model for the drift region that accounts for the Kirk effect.

In this paper, we present test structures and procedures to characterize and model mismatch of the breakdown voltage of Zener diodes. Direct force-current/measure-voltage for breakdown is not sufficiently accurate for mismatch characterization, so we use an $I(V)$ sweep followed by cubic interpolation; the accuracy of this approach is verified using the Tuinhout DUT-1-2-1-2 methodology. To demonstrate our approach, we present measured and modeled breakdown voltage mismatch for 5 V Zener diodes in a 90 nm power BCD process.

A method for modeling the distributive effects of RC transmission line is developed which is applicable to cases in which one end or both ends are connected to the input signal. Nonuniform recursive segmentation is used. The segments are categorized into three types, with each modeled by a distinctive and asymmetric lumped circuit in $\pi $ topology. The number of segments is determined by the frequency range required. The new method is applied to model the distributed MOSFET gate and bipolar junction transistor base. Both frequency and transient response characteristics are much better modeled compared with existing methods.

This paper studies the phase diagram of source pinchoff of dual-gate JFETs and presents a source pinchoff modeling formalism that is smooth across the phase boundaries. Based on this, an $I_{\textrm {ds}}$ model is derived, which is numerically robust for any value of top- and bottom-gate voltages. The method is applied to both the exact model for $I_{\textrm {ds}}$ and an approximated form based on mid-point-potential linearization, and is verified by comparison with numerical simulation. Modeling of short-channel effects is included.

This paper presents an accurate and computationally efficient method to calculate the drain–source saturation voltage $V_{\mathrm{ dsat}}$ of dual-gate (i.e., four-terminal) junction field-effect transistors. The method accounts for velocity saturation and for channel thickness modulation by any combination of MOS or p-n junction gates. In three iterations, it achieves an error of less than 2%. Our algorithm converges significantly faster than the direct application of the Newton–Raphson method because of careful selection of an initial value and the leverage of the convex and concave nature of the curves whose intersection defines $V_{\mathrm{ dsat}}$ . The method is applied to both the exact model for $I_{\mathrm{ ds}}$ and an approximated form based on mid-point-potential linearization, and is verified by comparison with numerical simulation.

This paper presents a new compact model, JFETIDG, for independent dual-gate JFETs. The model is applicable to JFETs with any combination of p-n junction or MOS gates, captures geometry and temperature dependencies. As a special case, it can model junctionless MOSFETs. The model is verified by comparison to experimental and TCAD data. Verilog-A code for the model is available in the public domain.

This paper examines the impact of quasi-ballistic transport (QBT) on bipolar transistor (BJT) intrinsic terminal current noise by analytically solving the general 3-D minority carrier noise transport equation using Hansen's nonhomogenous boundary conditions with extensions to include injection noise. Transistor noises are further expressed in Y-parameters, as was done in the widely used van Vliet model, with extra corrections accounting for QBT. For 10-nm base width of BJTs without base built-in field, while QBT is significant in affecting IC, Sic is shown to be less than but close to the classic 2qIC.

A new approach to implementing correlated high-frequency noise in bipolar junction transistor (BJT) large-signal compact models is developed by placing an RC -delayed noise current between the base and collector nodes. The approach reproduces the two stages of noise transport in a BJT, i.e., noise generation in the base and emitter and transportation through the collector-base junction space-charge region (CB SCR). The frequency dependence of the intrinsic noise sources due to the CB SCR is fully described with an accuracy value up to the second order of ω. As an example, the negative frequency dependence of Sic is correctly described for the first time. The approach is applicable to any large-signal compact model, and it is demonstrated using measurement data in both InGaP/GaAs heterojunction bipolar transistors (HBTs) and SiGe HBTs.

This paper models the input non-quasi-static (NQS) effect of bipolar transistors using charge partitioning. The input NQS effect associated with the base minority carrier transport is modeled with a RC network, while the input NQS effect associated with the base-collector space charge region (CB SCR) carrier transport is modeled with a RLC network. With the proposed input NQS equivalent circuit model, Y-parameters and RF noise parameters using the van Vliet model are successfully modeled for frequencies up to fT. The transport noise model is extended to represent the van Vliet model by using two noise related time constants, which eliminates the need of Y-parameter in the description of the noise source. The input NQS effect for such model is verified to be important only for frequencies above fT/3. Analytical Y-parameter and noise solutions of a 1-D bipolar transistor at low injection level are used for validation.

The general van Vliet noise model for transistors was derived for base minority carriers only under adiabatic boundary conditions. This paper extends the model by including the emitter minority carrier noise and the base–collector space charge region (CB SCR) effects based on the mathematical framework developed by van Vliet. Both the finite surface recombination velocity at polysilicon emitter and the finite carrier exit velocity at CB SCR are considered. It is proved that the van Vliet model can be directly used to include the emitter minority carrier noise, and the model holds when the two finite velocity boundary conditions are imposed. A new set of equations are derived to include the effect of CB SCR delay on noise.

This paper presents modeling of correlated RF noise in the intrinsic base and collector currents of SiGe heterojunction bipolar transistors using quasi-static equivalent circuits. The noises are first extracted from measured noise parameters using standard noise circuit analysis. Using the extraction results, model equations are proposed to describe both the frequency and bias dependence of the correlated noise sources using a single set of model parameters. The model is demonstrated using noise data from both measurement and microscopic noise simulation. The model is shown to work at frequencies up to at least half of the peak f/sub T/ and at biasing currents below high injection f/sub T/ rolloff.

We examine here the physics and implications of minority carrier injection induced dopant deionization in bipolar transistors. At low temperatures, the rate of such deionization with increasing bias is significant in the neutral base of SiGe HBTs doped at a level near Mott transition, and charge control based transit time equations need to be modified properly. The total charges associated with conduction band, integral of q(n − N+ d ), and the total charges associated with valence band, integral of q(p − N− a ), replace the total electron and hole charges in transit time equations. Another consequence is that considerably less hole charge is induced by the injected electron charge in the neutral base, which has implications on both device analysis and compact modeling.

Four-port on-wafer de-embedding is necessary for on-wafer measurement at frequencies above 50 GHz. We found notable discrepancy between the Y-parameters de-embedded using different options provided by a recently published general four-port de-embedding algorithm to solve the four-port Y-parameter matrices. The problem is caused by the ideality assumptions on the internal THROUGH test structure. In this paper, we develop a further generalized algorithm that drops any ideality assumption except passivity on the THROUGH structure. The new method works for transistor S-parameters with or without Impedance Standard Substrate calibration.

This paper presents an improved algorithm to solve the general 4-port parasitics de-embedding problem. Experimental results on 0.13 mum RF CMOS device are presented. For the device examined, gate resistance extracted from open-short results is 40% lower than that extracted from 4-port results. The reciprocity and symmetry of the 4-port parasitics are also examined

This paper examines the impact of collector-base space charge region (CB SCR) on RF noise in scaled bipolar transistors by solving the Langevin equation of electron noise transport. The van Vliet model, which was derived for intrinsic base only, was evaluated for scaled bipolar transistors in which CB SCR transit time is most significant. An improved noise model accounting for CB SCR effects is derived.

This paper investigates the impact of fringe BE junction on base majority carrier RF noise in SiGe HBTs. Due to fringe effect, the base hole noise should be modeled by correlated noise voltage source and noise current source in hybrid representation. The noise voltage source can be modeled by a weakly bias dependent noise resistance that is different from the intrinsic base resistance. The correlation between the two noise sources is important for biases around peak fT.

This paper investigates the emitter geometry scaling of RF noise in SiGe HBTs based on noise measurements. The extracted intrinsic noise using noise de-embedding method is found to scale ideally with emitter area and is the major noise source. Non ideal scaling of noise parameters is found to be mainly from the non ideal scaling of base resistance. A recently proposed semi-empirical noise model is examined for its scaling ability.

The input non-quasi-static (NQS) effects in SiGe HBTs are analyzed using Taylor series expansions of intrinsic Y-parameter expressions. The input NQS effect is shown to strongly affect extraction of the intrinsic base resistance and hence NF/sub min/ modeling.

A new direct extraction method, using a set of Z-parameter based ratios, is developed for SiGe HBTs. The input non-quasi-static effect is included to enable more accurate noise modeling. Excellent fitting with experimental data is obtained up to 60 GHz over a wide range of biasing currents.

This work presents experimental extraction of intrinsic base and collector current noise of SiGe HBTs as well as their correlation. Using the extraction results, several widely used noise models are evaluated, including the conventional SPICE model, the Van Vliet model, and the transport noise model. Connections and differences between various models are discussed.