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A novel perpendicular spin-transfer torque magnetic random-access memory spin valve with a memory-cell size below 20 nm × 20 nm and a thermal stability factor Δ of ~77 (10-year retention time) was designed by ferromagnetically coupling a multiple free layer [Co/Pt]n to Co 2 Fe 6 B 2 having interfacial perpendicular magnetic anisotropy (i-PMA) instead of coupling to a conventional double i-PMA free layer (Δ = 33). Thermal stability (Δ) increased with an increase of n in the [Co(0.47nm)/Pt(0.23 nm)]n multiple free layer. In particular, Δ = 80 could be achieved with n = 4 for a 15 nm × 15 nm memory-cell size. However, the tunneling magnetoresistance (TMR) ratio, which should be above 150% to assure a reasonable sensing margin, rapidly decreased from 190% to 98% with an increase in n from 0 to 4. This decrease was associated with W and Pt atomic diffusion into the MgO tunneling barrier. Improvement in the crystallinity of the MgO tunneling barrier increased the TMR ratio to 144% for n = 4.

A perpendicular spin transfer torque (p-STT)-based neuron was developed for a spiking neural network (SNN). It demonstrated the integration behavior of a typical neuron in an SNN; in particular, the integration behavior corresponding to magnetic resistance change gradually increased with the input spike number. This behavior occurred when the spin electron directions between double Co2Fe6B2 free and pinned layers in the p-STT-based neuron were switched from parallel to antiparallel states. In addition, a neuron circuit for integrate-and-fire operation was proposed. Finally, pattern-recognition simulation was performed for a single-layer SNN.

A new design for high density integration greater than gigabits of perpendicular-magnetic-tunnel-junction (p-MTJ) spin-valve, called the double pinned (i.e., bottom and top pinned structures) p-MTJ spin-valve achieved a multi-level memory-cell operation exhibiting four-level resistances. Three key magnetic properties, the anisotropy exchange field (Hex) of the bottom pinned structure, the coercivity (Hc) of the double free-layer, and the Hc of the top pinned structure mainly determined four-level resistances producing tunneling-magnetoresistance (TMR) ratios of 152.6%, 33.6%, and 166.5%. The three key-design concepts are: i) the bottom pinned structure with a sufficiently large Hex to avoid a write-error, ii) the Hc of the double free-layer (i.e., ~0.1 kOe) much less than the Hc of the top pinned structure (i.e., ~1.0 kOe), and iii) the top pinned structure providing different electron spin directions.

These days dynamic-random-access-memory (DRAM) fabrication to scale down under 10-nm is complex which leads to high cost [1]. On the other hand, perpendicular spin-transfer-torque magnetic random access memory (p-STT MRAM) cell has a possibility of high-density integration with feature size of 4F2. Therefore, p-STT MRAM is the most powerful candidate of new memory instead of DRAM. In hence, p-STT MRAM requires high tunneling magnetoresistance (TMR) ratio greater than 150%, enough thermal stability (Δ=KuV/kBT) above 75 for a ten-year retention-time, and low switching current (J C0 ~ 1 MA/cm2) must be achieved for low power consumption [2-4]. However, the thermal stability is hard to maintain when the cell size is scaled down to 10 nm because the small volume of free layer leads to the changes of direction of spin by thermal agitation [5]. In this study, we designed a p-MTJ spin-valve with a double pinned structure to realize two-bit operation to overcome a larger scaling limit. We calculated four resistance states using relationship between the two different TMR of each MTJs. In particular, if the TMR of MTJ1 is half of MTJ2 and ratio of parallel resistance(Rp2/Rp1) is 0.8-0.9, the difference of each resistance state is equal. (see Fig. 1(b)) The TMR is mainly dependent on thickness of MgO tunnel barrier; therefore, we fabricated the p-MTJ spin-valve with a different thickness of MgO tunnel barrier (0.90 nm-1.35 nm) of MTJ1. Finally, we confirmed that the R-H curves match the four resistance states of p-MTJ with double pinned structure with our predicted results, and interval of resistance state is uniform when the thickness of top and bottom MgO are 1.36 nm and 1.10 nm as shown in Fig. 1(c). This implies that the double pinned p-MTJ spin-valve may be suitable for terabit integration compared to that of the single-bit operating p-STT MRAM memory cells. In the end, we report dependency of MLC behavior on thickness of top MgO tunneling barrier in double pinned structure pSTT MRAM. In addition, we present the MLC behavior of pSTT-MRAM with double pinned structure and show the thickness of top MgO for uniform resistance state. Acknowledgements This work was supported by Basic Science Research Program through the National Research Foundation of Korea (NRF) grant funded by the Korea government (MSIP) (No.2017R1A2A1A05001285) and Brain Korea 21 PLUS Program in 2014. References [1] K. C. Chun et al., IEEE J. Solid-st. Circ. 48, 598 (2013) [2] J. G. Park et al., IEEE Int. Electron Devices Meeting, IEDM 2015–February, 19.2.1-19.2.4 (2015) [3] Y.Huai et.al., IEEE International Magnetics Conference, AB-07 (2015) [4] H.-S. P. Wong et. al., “Stanford Memory Trends,” (2015) [5] Shouzhong Peng, et al., IEEE MAGNETICS LETTERS, volume 8 (2017). Figure 1