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We have fabricated a full-wave rectifier using fully depleted amorphous In-Ga-Zn-O thin-film transistors (TFTs). The rectifier is composed of four TFTs, and it rectified 13.56-MHz wireless input from a 200-mW commercial RFID reader/writer. We also have analyzed an output voltage and an operation frequency of the fabricated rectifier.

To screen candidate materials for dynamic random-access memory capacitors, the tunneling probability at a constant equivalent oxide thickness (EOT) of metal-insulator-metal (MIM) capacitors was theoretically maximized according to a tradeoff between permittivity and band offset. As a result, it was found that cubic HfO2 with a TiN electrode is a promising candidate. TiN/Al-doped HfO2/TiN MIM capacitors were fabricated by inserting Al2O3 layers for phase control of HfO2 and for suppression of TiN oxidation. The fabricated capacitors exhibit leakage current of 80 nA/cm2 at 1 V and EOT of 0.7 nm. Moreover, the main leakage current was estimated to originate from oxygen vacancies.

We investigated the effect of dopant profile engineering in planar MOSFETs, in which activation annealing was done using only nonmelt laser spike annealing (LSA). Device performance was 10% and 20% better compared to that when conventional LSA and rapid thermal annealing (RTA) are used, respectively. We achieved this by reengineering the following: 1) angle implantation in the extension of an nFET; 2) germanium preamorphization implantation in the extension of a pFET; 3) halo implantation with lower energy and smaller tilt angle; 4) deep source/drain by two-step implantation, and 5) counter implantation adjusted to the halo conditions. Hot carrier degradation was also reduced to an RTA-comparable level by halo profile engineering. Thus, we show that a submillisecond LSA is a promising technique for the fabrication of ultrashallow junctions for the 45-nm technology node and beyond and that a dopant profile engineering taking into account the minimal diffusion length of LSA is required to bring out the best device performance.

Charge localization causes initial retention loss and memory window narrowing after write/erase cycling in a nonvolatile memory device using a metal–oxide–nitride–oxide–semiconductor (MONOS) structure. To overcome these problems, we propose the use of silicon-rich silicon nitride (SRN) thin film as a charge-trapping layer. It was found that most of the electrons injected from the substrate were trapped at the interface between the SRN film and the top oxide and the number of electrons captured by bulk traps of the nitride is negligible. When negative bias is applied to the gate electrode, the electrons trapped at the top interface move back to the bottom interface with SRN. The high effective mobility of the electrons is presumably due to donor-like traps at 0.8 eV below the conduction band bottom of SRN.

A new long-wavelength-photosensitive self-assembled-monolayer (SAM) was developed, and a process fabricating alignment-free printable electrodes for flexible organic thin-film transistors (OTFTs) with the SAM was proposed. The SAM was degraded and its wetability was changed from hydrophobic to hydrophilic by irradiating it with UV light (>350 nm). The irradiated areas of SAM became more hydrophilic with tetramethylammonium hydroxide (TMAH) solution, which is a commercially available photoresist developer. Using the SAM and a back substrate exposure technique with TMAH rinsing, we can induce the self-alignment of solution-processed source/drain electrodes with respect to a gate electrode. A 20-µm-gap pattern of PEDOT was successfully formed by spin-coating on a plastic substrate.

One of the major challenges in advanced complementary metal oxide semiconductor (CMOS) technology is to achieve an adequate dopant activation at the polycrystalline silicon (poly-Si) gate/gate oxide interface to minimize the poly-Si depletion effect. We investigated gate pre annealing by laser thermal process (LTP) in conjunction with laser spike annealing (LSA) source/drain (S/D) activation to effectively suppress poly-Si gate depletion while forming highly activated ultra shallow junctions for S/D. We found that carrier concentration at the poly-Si gate/gate oxide interface increases and, accordingly, electrical inversion oxide thickness (Tinv) decreases whereas dopant penetration into the Si substrate is suppressed to a level far below that in conventional rapid thermal annealing (RTA). We realized improved device performance characteristics such as a high drive current, a small threshold voltage (Vth) shift, and a reduced off current (Ioff).

The conventional theory of work functions (Schottky barriers) does not work at pure-metal/high-k-dielectrics interfaces. This occurs due to the selective interface atom bonding reflecting the large ionicity of high-k materials and the characteristic density of p-metal electronic states. Taking into accounts these features, we have constructed a new theory of work functions based on a concept of generalized charge neutrality levels. This theory systematically explains work functions of various gate materials on high-k dielectrics, in particular the unusual behavior of p-metal work functions, and naturally reproduces band offsets at various semiconductor/semiconductor interfaces.

Ultra-thin single crystal silicon with the (100) surface formed by the local-oxidation-of-silicon (LOCOS) on a silicon-on-insulator (SOI) substrate becomes a quasi-direct band-gap semiconductor due to the quantum mechanical confinement effect. The device is a simple pn diode in a planar structure. Electro-luminescence (EL) has been observed by the lateral carrier injections into the two-dimensional quantum well.

We have theoretically investigated poly-Si and metal gates on Hf-related high-k gate dielectrics. First, we have investigated the cause of the substantial threshold voltage ( V th ) shifts observed in Hf-related high- k gate stacks with p+poly-Si gates. The oxygen vacancy ( Vo ) level in ionic HfO 2 is located in a relatively higher part of the band gap. If the p+poly-Si-gate is in contact with HfO 2 , Vo formation in the HfO 2 induces a subsequent electron transfer across the interface because of the higher energy level position of Vo , causing a substantial V th shifts in p+poly-Si gate MISFETs. Next, we also investigate the microscopic electronic structures at metal gates/HfO 2 interfaces. We have found that the wave functions of metal induced gap states (MIGS) have large amplitudes both around Hf and O atoms, which may be the cause of unusual work function behaviors of p-like metals. INTRODUCTION The considerable downscaling of Si devises has brought about the requirement for a continuing need for significant reduction in gate dielectric film thickness, and even current commercial based large scale integrated (LSI) circuits have SiO

We have investigated theoretically the cause of the substantial threshold voltage (Vth) shifts observed in Hf-related high-k gate stacks with p+poly-Si gates, by focusing on the ionic nature of HfO2. The oxygen vacancy (Vo) level in ionic HfO2 is located in a relatively higher part of the band gap. This high position of the Vo level results in a significant elevation of the Fermi level for p+poly-Si gates, if the p+poly-Si gate is in contact with the high-k HfO2. Vo formation in the HfO2 induces a subsequent electron transfer across the interface, causing a substantial Vth shifts in p+poly-Si gate MISFETs. Moreover, our theory also systematically reproduces other recent experimental results.

We have proposed an area-selective post-deposition annealing (PDA) process that involves a combination of flash lamp annealing and the use of a Si photoenergy absorber (Si-PEA) for metal/high-k gate last metal–insulator–semiconductor field-effect transistors (MISFETs) with NiSi on source/drain (S/D). The process makes it possible to suppress the increase in both the sheet resistance and junction leakage current of NiSi S/D regions. This PDA process also showed optimality for silicide gate electrode formation with silicidation of part of the Si-PEA. It was found that the flash lamp PDA with Si-PEA on nickel–silicide/HfAlOx/SiO2 gate-last MISFETs reduced electron trapping at the gate dielectric and resulted in better PBTI immunity than conventional rapid thermal PDA and flash lamp PDA without Si-PEA.

Changes in optical thickness and equivalent oxide thickness (EOT) during postdeposition annealing (PDA) and postnitridation annealing (PNA) were investigated to fabricate sub-1-nm-EOT nitrided hafnium silicate (HfSiON) gate dielectrics. In spite of optical thickness reductions by PDA, none of the PDA conditions could reduce the EOT and bring about the merit in leakage current reduction. On the other hand, high-temperature PNA without oxygen was found to be effective for reducing both optical thickness and EOT. Furthermore, leakage current reduction ratio and effective mobility were improved by applying high-temperature PNA. Consequently, the fabrication of 0.81-nm-EOT HfSiON gate dielectrics with a gate leakage current of 0.74 A/cm2 at 0.7 V and an electron mobility of 235 cm2/(V s) at 0.8 MV/cm (76% of SiO2) has been realized.

The effects of the nitrogen profile in the SiON-interfacial layer (IL) on the mobility in FETs employing a HfAlO/SiON gate dielectric have been investigated. In order to suppress the interdiffusion between HfAlO and SiON, the nitrogen concentration in SiON should be higher than 15 at%, while the substrate interface should be oxygen-rich in order to suppress the mobility reduction. By using an NO reoxidation of NH/sub 3/ formed 0.4-nm-thick silicon nitride, the mobility reduction due to the SiON-IL was successfully suppressed, and electron and hole mobility of 92% and 88% of those for SiO/sub 2/ at V/sub g/=1.1 V were obtained for HfAlO/SiON with equivalent oxide thickness (EOT) of 1.1 nm. By using nitrogen profile engineered SiON-IL, good equvalent oxide thickness (EOT) uniformity, low EOT, low gate leakage current, low defect density, and symmetrical threshold voltage were all achieved, indicating that a poly-Si/HfAlO/SiON gate stack would be a candidate as an alternative gate structure for low standby power FETs of half-pitch (hp)65 and hp45 technology nodes.

We have constructed a universal theory of the work functions at metal/high-k HfO2 and La2O3 dielectric interfaces by introducing a new concept of generalized charge neutrality levels. Our theory systematically reproduces the experimentally observed work functions of various gate metals on Hf-based high-k dielectrics, including the hitherto unpredictable behaviors of the work functions of p-metals. Our new concept provides effective guiding principles to achieving near-band-edge work functions of gate metals. Moreover, we discuss the potential of the new high-k dielectrics of La2O3 based on this new concept.

The interface reaction between poly-Si and high- k dielectrics (including HfSiON and HfAlO) have been investigated using hard X-ray ( hν = 5.95 keV) photoemission spectroscopy (HX-PES). HX-PES method has enabled us to probe intrinsic interfacial states without surface conditioning, due to the large escape depth of high energy photoelectrons. From the results of take-off angle dependent data (O 1s and Si 1s core level photoemission spectra), we have found the difference of interfacial reaction concerning poly-Si and high- k dielectrics for their fabrication process. The oxidation proceeded near to surfaces by the difference in the existence of doped boron atom and in the annealing temperature for fabrication process.

We propose new test device structures, Gate-Last-formed structures, which are suitable for fundamental study of high-k gate insulator or metal gate electrode MISFETs. The gate insulator and electrode stack is formed after local interconnect pads connected with source and drain. The gate stack is build in trench formed by dry and wet etching and is non-self-aligned to the source and drain. The wet etching restricts damage formation on the exposed Si surface underneath the trench. Electrical characteristics are measurable just after exposure of surface of the local interconnect pads without conventional Al wiring. This structure can provide methods both for fundamental evaluation and for material selection of new gate stack materials by investigation of MISFET characteristics. This is achieved with short TAT and avoiding contamination penalty to a fab.

The reaction behavior of the Interfacial Layer (IL) in an HfAlOx/SiO2 and SiON structure during a post deposition annealing (PDA) in an N2-diluted oxygen ambient was examined. After a PDA at 1,050oC for 1 s, the 0.7 nm-thick IL was reduced if the O2 concentration was lower than 0.02%. The reduction of the IL led to the formation of defects and the Si migration to the HfAlOx surface, resulting in an increase in the C-V hysteresis. The amount of Si migrated to HfAlOx surface decreases with increasing the O2 concentrations during PDA and changing the interfacial layer from SiO2 to SiON. Even if SiON is used for interfacial layer, the decreasing of mobility was caused by nitrogen which stay in interface between SiON and substrate. Optimization of nitrogen in SiON interfacial layer is necessary. Electron and hole mobility of 75/77% of that for SiO2 were obtained for HfAlOx/SiON with EOT = 1.6 nm because of optimization of PDA O2 concentration and nitrogen profile in SiON.

Changes in transient capacitances during application of step voltages to the gate electrode of metal-oxide-semiconductor (MOS) structures with stacked gate dielectrics were investigated. The behaviors of the changes in transient capacitance varied depending on the thickness of high dielectric films. The results indicate that negative charges were trapped near the gate electrodes during stress voltage application, while positive charges were trapped near the Si/SiO2 interface. These charges in gate films were released at different time constants during relaxation.

3–7-nm-thick HfAlOx (Hf/Hf+Al=29%) films were deposited on thermally grown ~0.9-nm-thick SiO2/Si(100) by atomic layer chemical vapor deposition (ALCVD) at 350°C. After postdeposition anneal (PDA) in 0.2% O2 ambience at 1050°C for 1 s, we evaluated the compositional profile of HfAlOx/SiO2 dielectric stack structures by X-ray photoelectron spectroscopy (XPS) in combination with oxide thinning in a dilute HF solution and observed Si diffusion and incorporation into the HfAlOx network by a few at.% through the pregrown SiO2 layer. The energy band alignment in the dielectric stack structure on Si(100) after the PDA was determined by the energy band gap of the ALCVD HfAlOx films and the valence band offset at the interfaces between HfAlOx and Si(100), which were measured by analyzing the energy loss spectra of O1s photoelectrons and the valence band spectra of the dielectric stack structures, respectively. Also, by the total photoelectron yield spectroscopy (PYS) of the dielectric stack structures, filled defect states as many as 1–3×1017 cm-3 eV-1 were estimated in the HfAlOx layer in the energy region of 0.4 to 0.8 eV from the energy position corresponding to the Si valence band top.

Thin Hf0.3Al0.7Ox films fabricated by an atomic-layer-deposition technique were characterized using monoenergetic positron beams. From the measurements of the Doppler broadening spectra of annihilation radiation and the lifetime spectra of positrons for 3- and 7-nm-thick HfAlOx films deposited on SiON(0.9 nm)/Si, it was found that positrons in the HfAlOx films annihilate from the trapped state by open spaces that exist intrinsically in their amorphous structure. The line-shape parameter S and the positron lifetime corresponding to the HfAlOx films decreased with increasing oxygen content (0.004–1%) in the annealing atmosphere. This fact was attributed to the shrinkage of the open spaces due to the change in the matrix structure of amorphous HfAlOx. The increase in oxygen content was also found to decrease the transient current of n+-polycrystalline-Si/HfAlOx/SiON/Si. The decrease in the mean size of the open spaces and the resultant hardening of the matrix structure are considered to suppress the dielectric polarization of HfAlOx.

The effects of introducing NH3/Ar plasma pulses during the atomic layer deposition (ALD) of HfAlOx films and during the in situ nitridation of an interfacial layer (IL) on the properties of HfAlOx-FETs were investigated. The interaction between HfAlOx and IL and the dopant penetration were suppressed by the introduction of a NH3/Ar plasma pulse during ALD, because it increases the nitrogen content at the interface of HfAlOx/IL. Moreover, the nitrogen content in the IL could be controlled by adjusting the number of NH3/Ar plasma pulses used for in situ nitridation. No threshold voltage shift due to the nitridation of the Si substrate was observed, indicating that the nitrogen profile was well controlled when using a NH3/Ar plasma pulse for in-situ nitridation. It was found that in-situ nitridation with 5 cycles of NH3/Ar plasma pulses was optimum for reducing C–V hysteresis and improving carrier mobility.

The effect of high gate-leakage current on the accuracy of mobility evaluation was investigated. This investigation showed that a high gate leakage current makes it difficult to measure the mobility accurately in the case of using a conventional equivalent circuit with lumped circuit elements. To measure the mobility accurately, the authors therefore used a transmission-line model. Its validity was experimentally confirmed by using the capacitance-frequency characteristic of the gate of MOSFETs. The transmission-line model shows that a high gate-leakage current induces a voltage distribution in the channel, which causes a serious error in the mobility evaluation. Accordingly, a precision parameter, which clarifies the relation between channel length and measurement error, was defined. This parameter was then used to define a criterion for channel length for accurately measuring mobility. The channel-length criterion was used to successfully evaluate the mobility of n-MOSFETs with gate dielectrics of 1.4-nm-thick oxynitride (SiON).

We have examined the effects of phase separation on the inversion electron mobility of metal-insulator-semiconductor field-effect transistors with high-permittivity (high-κ) gate dielectrics. On the basis of experimental data of hafnium silicate films, we developed a phase separation model of a high-κ film that contains crystal grains of high permittivity in an amorphous film of low permittivity. Using this model, we calculated the electron mobility by applying a linear response theory and found that the phase separation results in a significant reduction of the electron mobility. We also discuss the differences in the calculated electron mobility between the phase-separated hafnium silicate and hafnium aluminate.

The advantage of using the Al 2 O 3 gate dielectric is discussed from thermodynamic and kinetic standpoints. We fabricated n-field effect transistors with Al 2 O 3 dielectrics and built-in interfacial SiO 2 having thicknesses of 0.6-2.0 nm to investigate the effect on electron mobility and gate leakage current. The mobility was reduced and the shift in flat-band voltage was increased with decreases of the thickness of the interfacial SiO 2 . We propose that a fixed charge is generated at the interface of Al 2 O 3 / interfacial SiO 2 , it induced Coulomb scattering to the surface channel, and that the electron mobility is consequently reduced. The plot of gate leakage current against the total physical thickness, which includes Al 2 O 3 and interfacial SiO 2 dielectrics, showed the enhanced leakage current. This suggests that the band offset may be lowered at the interface of ultra-thin SiO 2 /Si beneath the Al 2 O 3 dielectric.

We investigated the transistor properties and electron mobility of n-field-effect transistors with Al2O3 gate dielectrics. Post-deposition annealing was conducted at a reduced oxygen pressure to form a thermally stable interfacial oxide that was as thin as possible. The characteristics of the field effect transistors are predetermined by the interface and are dependent on the oxidation conditions. The electron mobility is reduced to half that of conventional SiO2 dielectrics. We propose that fixed-charge-induced Coulomb scattering is responsible for the reduced mobility.

A titanium oxide film was deposited on a silicon substrate by RF-magnetron sputtering using a sintered oxide target in an argon-gas atmosphere. Phase transition and crystallization during the post-heat treatment were investigated. The thermodynamic stability of phase, oxygen diffusion through the film to form an interfacial SiO2 layer, and the reaction process in which the rutile-type TiO2 is crystallized were investigated. Rock-salt-type TiO with large deficiency of titanium ions is quenched in the as-deposited film in non-equilibrium. The following post-heat treatment in nitrogen gas transforms the film to Ti3O5, while post-oxidation transforms the film into rutile-type TiO2, even in an ultra-thin film of 5 nm, at the expense of the growth of interfacial SiO2 with a thickness of 2.5 nm. The growth of the interfacial oxide is explained in terms of three origins: oxygen defects incorporated into the rutile-type TiO2, fast oxygen diffusion via the defects, and the fact that non-stoichiometric TiO2 − x is less stable than SiO2. We also discuss the main criteria that must be satisfied in order to apply the high-permittivity oxide to a gate insulator.

We investigated rutile-type titanium dioxide (TiO2) films for possible use as a high-k gate insulator. The TiO2 thin films were directly deposited on Si substrates using a RF magnetron sputtering method with a sintered oxide target. A single phase of rutile-type TiO2 whose dielectric constant of approximately 75 was obtained when the film was deposited in an inert gas atmosphere and annealed at 800 °C in an oxidizing gas atmosphere. The oxygen ions were deficient in the as-deposited film, and consequently, a sufficient oxygen supply was needed to crystallize the film to a single phase of rutile during the post-annealing. However, the interfacial SiO2 layer between the TiO2 and the Si substrate simultaneously grew thicker than 2 nm. As the interfacial SiO2 grew, the leakage current was decreased and the equivalent oxide thickness was increased, in the Au/rutile-type TiO2/Si capacitor. Therefore, we concluded that the growth of the interfacial SiO2 layer thicker than 2 nm is inevitable to form the single phase of rutile-type TiO2 and to decrease the leakage.

Reliability issues regarding scaled silicon devices are reviewed from the viewpoint of the 100-nm technology node. Topics covered include hot carrier degradation, negative bias-temperature instability, boron penetration, interface properties of a high-k dielectric film, and stress-induced leakage current of a floating-gate-type non-volatile memory. Soft error by terrestrial neutrons is also discussed as an emerging reliability issue. In addition, copper-wiring reliability is extensively reviewed from the viewpoint of further miniaturization.

The occurrence of switching-induced suppression of the remanent polarization (fatigue) in Pb(Zr,Ti)O3 (PZT) ferroelectric capacitors with comb shaped top electrodes was studied by means of scanning force microscopy assisted by a lock-in amplifier. Fatigue occurs earlier in capacitor with narrower comb-fingers, mainly in the central part of the fingers. In addition to this size effect, electrode-edge effects could be observed. Along the edges, in an area of about 250nm width, the preferential direction of the blocked polarization is opposite to that in the center of the comb fingers; in this area, fatigue occurs generally one to two cycle-decades later. Self-recovery effects were also localized to mainly occur near the edges of the electrodes. The mechanism of these results is discussed on the basis of fringe field and stress at top electrode edge.

Microstructures (texture and grain size) dependence of PZT thin films on the oxidation state of lead, heating rate of crystallization annealing, and the quality of bottom electrode was discussed. The spatial variations of the switching charge for a PZT capacitor is mainly determined by the texture of PZT thin film. Switching charge variation less than ±2% is achieved by making a film highly [111] textured.

The Pt/PbZrxTi1−xO3 (PZT) interfacial reaction caused by low-temperature (320 °C) annealing and resulting change in the surface Fermi level position (Schottky barrier height) has been studied by using in vacuo x-ray photoelectron spectroscopy (XPS). A thin (2 nm) Pt layer was deposited on a polycrystalline PZT film and annealed in 0.5-Torr H2 and O2 in a chamber connected to the XPS chamber. For the PZT samples annealed prior to Pt deposition, a small amount of metallic Pb was produced after the Pt deposition. The annealing also moved the surface Fermi level (EF) at the Schottky interface toward the conduction band minimum (EC) of PZT by 0.4 eV, as evidenced by the band-bending shift of the PZT core levels. Excess metallic states appeared in the valence-band spectra of an annealed bare PZT surface. There was no appreciable annealing-atmosphere dependence in the amount of metallic Pb produced and surface EF position at the PT/PZT interface. However, a clear annealing-atmosphere dependence was observed for ...

Effects of nitrogen incorporation on suppression of electron charge traps in Hf-based high- kappa gate dielectrics have been studied by first-principles calculations, focusing on interactions between N atoms and electrons trapped at oxygen vacancies (VO's). Our total energy calculations revealed that the formation energy of a doubly occupied state of VO is significantly increased in HfOxNy compared to that in HfO2 . This clearly indicates that the electron charge traps at VO's are considerably suppressed by N incorporation

We investigated the effects of thin film interference during sub-millisecond annealing on junction activation and recrystallization using ultra-thin-body silicon-on-insulator (UTB-SOI) wafers. We showed that, in the wavelength range used by broadband heating sources in flash lamp annealing (FLA), thin film interference in the body Si and buried oxide layers of UTB-SOI wafers can change the light absorption. This in turn reduces the duration of the heat distribution, resulting in insufficient activation of junctions during sub-millisecond annealing. Further, we showed that laser spike annealing (LSA) can achieve full activation of junctions even in UTB-SOI wafers because using light waves in the far-infrared wavelength region can minimize thin film interference.

In the stacked structure of PbZr1-xTixO3(PZT)/Pt/TiN/poly-Si for a ferroelectric random access memory (RAM), the mechanism of TiN barrier-metal oxidation was investigated by transmission electron microscopy (TEM). In the cross-sectional TEM images of PZTyPtyTiNySi, titanium oxide was observed beneath the Pt grain boundary. The oxygen was diffused through the Pt grain boundary during the heat treatment in an oxygen atmosphere for crystallization of PZT films. The annealing of the TiN film in ammonia resulted in the suppression of the oxidation during the crystallization annealing of PZT. The minimum required Pt film thickness to protect TiN from oxidation can be reduced from 200 nm to 100 nm.

The role of ozone in the reactive coevaporation of the lead zirconate titanate thin film was investigated by depositing films at various growth rates with various ozone fluxes or molecular oxygen fluxes on unheated substrates and then crystallizing them using rapid thermal annealing. The oxidation state of lead in the as-deposited film was determined from the ratio of the ozone to the total metal fluxes. The amount of atomic oxygen supplied to the surface of the film was at least 103 times larger when the deposition was done using ozone rather than molecular oxygen. When the ozone flux was more than one-third of the total metal flux, well-oxidized films were obtained. To ensure obtaining well-oxidized film, the ozone flax should be more than twice as much.

Physical properties of F-center in HfO 2 have been investigated by first-principles calculations. The F-centers (doubly occupied oxygen vacancy V o ) are found to generate gap states at 1.05 eV below the bottom of HfO 2 conduction band and they are remarkably elevated by extracting electrons from the F-center. The negative-U behavior of F-centers in HfO 2 is very different from those in the ionic rocksalt oxide such as MgO or CaO, which possesses positive-U character. The reason for this unique behavior of F-centers in HfO 2 is considered to be due to highly positively ionized Hf4 + ions, which are largely relaxed outward away from singly occupied or non-occupied F-centers. This outward relaxation is the origin of the remarkable elevations of the F-center levels. Moreover, similar negative-U behavior is also observed in HfON.

A one-mask-patterned ferroelectric capacitor test structure designed with a 0.5-μm feature size was fabricated. Oxygen plasma treatment after dry etching decreased the leakage current to as low as that of as-deposited film. These one-mask-patterned ferroelectric capacitors, with switching charge almost equal to as-deposited film, were successfully fabricated. Ferroelectric memories as dense as dynamic random access memories will become possible with this technology. However, the leakage current density for micron-sized capacitors is 2 to 10 times that of large capacitors. The leakage current in small capacitors is increased due to perimeter leakage that runs through the damaged region on the capacitor sidewall. © Scripta Technica, Inc. Electr Eng Jpn, 121(1): 43–50, 1997

A one-mask-patterned ferroelectric capacitor memory cell structures designed with a 0.5-μm feature size were fabricated. Oxygen plasma treatment after dry etching decreased the leakage current to as low as as-deposited film. The one-mask-patterned ferroelectric capacitors with switching charge almost equal to as-deposited film were achieved. Ferroelectric memories as dense as dynamic random access memories will become possible with this technology.

Lead zirconate titanate (PZT) thin films were prepared by reactive coevaporation with high-concentration ozone. PZT thin films that demonstrate the highest charge storage density (280 fC/μm2 at 1.5 V for 75-nm-thick film) yet reported have been fabricated. No fatigue was observed after 1011 polarization switching cycles even though a Pt electrode is used. A low leakage current of

Chemical states and structures of thin degenerated layers grown on the surface of PZT(Pb(Zr, Ti)O 3 ) films are investigated by X-ray photo-electron spectroscopy (XPS) and RHEED (reflection of high energy electron diffraction). A careful study of the Ti 2p peak in the XPS spectrum reveals that PZT films easily absorb moisture from the air and decompose into their component oxides. This creates a degenerated layer that can be removed by the nitric acid treatment. After this treatment, the PZT surface becomes more resistant to humidity than the original surface.

Deuterium was incorporated into the HfAlOx /SiON gate dielectric by the use of heavy water (D/sub 2/O) instead of H/sub 2/O in the atomic layer deposition (ALD) process of HfAlOx. The HfAlOx formed by D/sub 2/O-ALD acts as a deuterium reservoir, and the deuterium atoms are effectively incorporated into the SiON after full CMOS processing. It is clarified that the deuterium incorporation suppresses interfacial trap generation and interfacial SiON breakdown, while charge-trapping in the HfAlOx bulk traps is barely affected. The D/sub 2/O-ALD process is useful for improving the interfacial layer reliability under gate negative stress; therefore it is not only effective for HfAlOx, but also for high-/spl kappa//SiO/sub 2/(SiON) gate stacks with other high-/spl kappa/ materials such as HfO/sub 2/ or HfSiON.

The mechanism of TiN barrier metal oxidation of Pt/TiN electrodes are investigated for planarized stacked memory utilizing lead zirconate titanate (PZT). Thinner (

A theoretical investigation has been made of the origin of substantial threshold voltage (Vth) shifts observed in p+poly-Si gate Hf-based metal insulator semiconductor field effect transistors (MISFETs), by focusing on the effect of oxygen vacancy (VO) formation in HfO2. It has been found that VO formation and subsequent electron transfer across the interface definitely causes substantial Vth shifts, especially in p+poly-Si gate MISFETs. Moreover, the theory also systematically reproduces recent experimental reports that large flat band (Vfb) shifts are observed, even in intrinsic poly-Si gates, and that the Vfb shifts exhibit a high dependence on HfSiOx thickness.

We examined effects of the remote surface roughness, which is the roughness between the polycrystalline silicon gate and gate dielectric, on the inversion carrier mobility of metal-insulator-semiconductor field-effect-transistors with ultrathin gate dielectrics. We calculated the effective mobility by the linear response theory and found that the scattering from the remote surface roughness reduces the effective mobility especially at high vertical fields. The effective mobility is severely reduced, if the correlation length of the remote surface roughness is comparable to the inverse of thermal de Broglie wave number. We show that the hole mobility reduction experimentally found for the transistor with the Al2O3 gate dielectric can be explained by this scattering.

This paper presents results of statistical analysis of RTN in highly scaled HKMG FETs. A robust algorithm to extract multiple-trap RTN is proposed and applied to show that RTN can cause serious variation even when HKMG and undoped channel are introduced. We further focus on hysteretic behavior caused by RTN with time constants much longer than the circuit timescale. This reveals that RTN also induces novel instabilities such as short-term BTI and logic delay uncertainty. Extraction of RTN in SRAM arrays is also presented to discuss its impact on operational stability.

We have proposed an alternative approach for developing a steep subthreshold swing FET that is less than the theoretical diffusion-based limit of 60 mV/decade at room temperature. Instead of using a simple IGFET, we formed a complex device in a “single device” and worked it as a sub-circuit, which resulted in a steep subthreshold swing. We formed a tunnel junction in a drain diffusion layer of the MOSFET so that we could stuff a tunnel-injection bipolar, a resistor, and a MOSFET inside a single “scaled MOSFET”. We used device simulation to clarify the concept of “device complex”. Results showed a steep subthreshold swing even if the supply voltage was low (∼0.2 V).

The thin films of relaxor solid solution xBaZrO3 - (1-x)PbTiO3 (abbreviated to BPZT) withx=0.45 have been successfully fabricated by rf-magnetron sputtering. Crystallization behavior of amorphous BPZT thin films during RTA were investigated. Because of fast heating rate and short soaking period, crystallized film is composed with very fine grains and contains high concentration of oxygen vacancies. To reduce the oxygen vacancy, activated oxygen was employed. High storage charge density of 46 fF/μm2 and low leakage current were realized for 60 nm thick BPZT thin film. The dielectric constant dependence on temperature is very small compared with other ferroelectric thin films.