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Voltage-control spintronics memory (VoCSM) is a spintronics-based memory that uses the voltage-control-magnetic-anisotropy (VCMA) effect as a selection method and the spin-Hall effect as a write method, and is a candidate for future nonvolatile main memory because of its advantages such as high density, low energy consumption, and robustness against read disturbance. In this paper, we demonstrate VoCSM with a self-aligned heavy-metal electrode, which is the most desirable in mass production and can expect the lowest critical current ( $I_{C})$ due to its narrow electrode structure. We obtain the value of $I_{C}$ of around $400~\mu \text{A}$ for a magnetic tunnel junction of size $35~{\mathrm{ nm}} \times 245$ nm by using a self-aligned heavy-metal electrode. The value is lowered to one-third that of the conventional VoCSM structure and is comparable with that of spin-transfer torque writing. Moreover, $I_{C}$ decreased due to the VCMA effect and reached $260~\mu \text{A}$ for $\text{V}_{\mathrm {MTJ}} = -0.8$ V. We also found that the diffusion spin current from the lateral region, which is the concern matter of this structure, did not contribute very much to the switching due to the extremely short spin diffusion length of the heavy-metal electrode. It indicates that VoCSM with a self-aligned heavy-metal electrode may lead to the production of high-density and low-energy-consumption memory.

Recently MRAM technologies have been intensively developed. This paper describes novel solutions using advanced MRAM for near future computing applications. Three beneficial applications with MRAM are presented: energy saving, data reliability and performance improvement.

We report a novel convolutional neural network (CNN) accelerator utilizing “voltage control spintronics memory” (VoCSM). High throughput processing is achieved by high speed in-“nonvolatile memory”-computation using high density VoCSM array. Since VoCSM has largest endurance even in short write pulse of all nonvolatile memories, write access speed can be increased. Also, density of processing element is higher than conventional SRAM based one, throughput is further increased. These technique reduces latency of CNN by 46% (ternary) and 73% (binary) compared to conventional CMOS processor with 8bit integer (INT8) for CIFAR-10 classification task. Also, energy is reduced by 72% (ternary) and 86% (binary).

Recently, STT-MRAM has been commercialized. MRAM with voltage controlled magnetic tunnel junction (VC-MTJ) has been expected as a post-STT-MRAM memory with faster speed and lower power [1–5]. Since read operation for VC-MTJ uses TMR as other MRAMs, conventional read can be used. On the other hand, VC-MTJ has specific write feature where write error rate (WER) is oscillatory dependent on pulse width. Hence, WER reduction for VC-MTJ is crucial. Previous studies have shown VC-MTJ applications for cache and main memory [6, 7]. Recently, storage class memory (SCM) has been introduced to mitigate memory gap between storage and main memory [8]. SCM is also a candidate for VC-MTJ utilization, since VC-MTJ has unipolar write suitable for 3D-crosspoint (3DX) configuration. This is the first paper to describe feasibility of VC-MTJ for SCM applications from the viewpoint of designs for memory cells and circuits. Typical SCM is characterized by 3DX structure with two-terminal selector device(SD) (Fig. 1(a)). SD has longer switching time than VC-MTJ [9–11]. Here, switching time variations of SD changes write pulse width of VC-MTJ that causes WER degradation. This is a major issue. To solve this, we propose a novel two-step pulse write method as described later. We evaluate WER improvement with this method by advanced circuit simulation. We further analyze WER reduction by interconnect and write driver. Major requirement for SD in 3DX memory is high on-off ratio to suppress sneak leakage current. Various SD have been intensively developed [9]. Among them, threshold type selector is considered to be promising due to large on-off ratio [10, [11] and several ten ns switching time. Figure 1(b) schematically shows conventional write pulse voltage $( \mathrm {V}_{\mathrm {W}})$, voltage across SD $( \mathrm {V}_{\mathrm {SEL}})$ and voltage across MTJ $( \mathrm {V}_{\mathrm {MTJ}})$. Initially, write voltage is applied to only SD, since off-state SD has much higher resistance than MTJ. After SD switches into on-state, write voltage is applied to only MTJ, since on-state SD has much lower resistance than MTJ. As SD has switching time variation, pulse width of $\mathrm {V}_{\mathrm {MTJ}}( \mathrm {T}_{\mathrm {MTJ}})$ varies and WER degrades severely. To suppress WER degradation, we propose two-step write pulse method (Fig. 1(c)), where write pulse has two voltage steps. First voltage is only for switching of SD and smaller than switch voltage of MTJ. Second voltage is for switching of MTJ. In this method, switch time variation of SD affects only the first voltage time, and not affects the second voltage time, $\mathrm {T}_{\mathrm {MTJ}}$. To evaluate WER with a proposed method, we firstly obtained $\mathrm {V}_{\mathrm {MTJ}}$ shape in 3DX arrays by circuit simulation based on 2X nm 3DX memory [8]. WER was then calculated using the $\mathrm {V}_{\mathrm {MTJ}}$ shape by Monte-Carlo simulation [3]. Figure 2 (a) shows WER of VC-MTJ in 3DX when 1024 bit cells are connected to a word line (WL). We calculated WER for various WL interconnect thickness, assuming interconnect material is tungsten [8]. The interconnect thickness was selected between 40 nm and 80 nm, since that of 3DX memory products is about 40 nm to 65 nm [8]. We also assumed damping constant, a = 0.025 and, diameter, f = 20 nm for MTJ, and external magnetic field to in-plane direction, $\mathrm {H}_{\mathrm {ext}}=152.6$ Oe, so that switching time is about 1ns. Fig. 2(a) also shows WER when an idealistic trapezoidal pulse having no interconnect delay is directly applied to VC-MTJ for reference. These results indicate that as interconnect becomes thicker, WER of VC-MTJ is improved, and it becomes closer to a target WER for SCM (~1×10−4). This reason is that the decrease in pulse rise and fall time by resistance reduction of interconnects. However, increasing interconnect thickness might make etching process difficult and obstacles further memory cell scaling. In case that interconnect thickness cannot be increased, we propose dual wordline (WL) driver circuit (DWD) shown in Fig. 2(b). When conventional single driver circuit is used for each WL, pulse distortion is largest at the other end. By driving WL from both ends using DWD, pulse rise and fall time become smaller than conventional ones. In this case, difference in activation time $( \mathrm {t}_{\mathrm {delay}})$ between the two WL drivers degrades WER (Fig. 2(c)), as shown in Fig. 2(d). When $\mathrm {t}_{\mathrm {delay}}$ is larger than 200 ps, WER becomes larger than single driver case. Therefore, we have to design interconnects and drivers so as $\mathrm {t}_{\mathrm {delay}}$ to be ~0s. WER is, then, almost the same as that of direct pulse application, as shown in Fig. 2(d). As a result, DWD circuit can reduce WER considerably close to a target WER for SCM (~1×10−4). These results thus indicate that WER of VC-MTJ for 3DX memory can be improved by proposed circuit designs. Figure 2(e) compares write performance of various nonvolatile memories, which indicates VC-MTJ is superior to others, since it has higher-speed and lowerpower write with higher-endurance compared with others. This work was partly supported by the ImPACT Program of the Council for Science, Technology and Innovation (Cabinet Office, Government of Japan). The authors would like to thank Yoichi Shiota for his contributions to VC-MTJ.

Our new proposal of voltage-control spintronics memory (VoCSM) in which spin-orbit torque in conjunction with the voltage-control-magnetic-anisotropy effect works as the writing principle showed small switching current of $37~\mu \text{A}$ for about 350 $K_{B}T$ switching energy. This indicates VoCSM’s writing efficiency is so high that VoCSM would be applicable for deep learning memories requiring ultra-low power consumption.

We propose a new spintronics-based memory architecture with 2 MTJs and 4 transistors as a unit cell for high-speed application. The architecture employs spin-Hall effect as a writing principle and voltage-control-magnetic-anisotropy (VCMA) effect as a write speed acceleration. We successfully demonstrated the unique complementary flash-writing scheme and proved a potential of ultrahigh speed writing with the prototype unit-cell and the test-element.

Voltage controlled magnetic tunnel junction (VC-MTJ) is fast as well as low power nonvolatile memory and it is expected to replace embedded (e-) working memory like SRAM.

Among various kinds of nonvolatile memory developed, spin torque transfer (STT)-MRAM has the highest write access speed and highest endurance (close to practically unlimited endurance). Hence, embedded (e-) STT-MRAM can cover various kinds of working memory applications that conventionally uses SRAM and e-DRAM. In advanced processors or SoCs, static power of SRAM and e-DRAM has been increased with CMOS scaling and becomes a major part of power consumed in those semiconductor chips. Although “Power gating (PG)” technique enables reduction in the leakage power of SRAM or eDRAM effectively, it can be used only when the memory data can be lost while application is not running (long standby state; >1us).

This paper presents voltage controlled MRAM (VCM) with novel fast read/write circuits for nonvolatile ultra-large last level cache. Further, write error rate has dramatically been reduced by thermal stability factor control using “continuous read-write-verify” scheme. Read error rate has also improved with “read-disturb-free non-destructive-self-reference read” with unipolar write of VCM.

Two performance gaps in the memory hierarchy, between CPU cache and main memory, and main memory and mass storage, will become increasingly severe bottlenecks for computing-system performance. Although it is necessary to increase memory capacity to fill these gaps, power also increases when conventional volatile memories are used. A new nonvolatile memory for this purpose has been anticipated. Storage class memory is used to fill the second gap. Many candidates exist: ReRAM, PRAM, and 3D-cross point type with resistive change RAM. However, nonvolatile last level cache (LLC) is used to fill the first gap. Advanced STT-MRAM has achieved sub-4ns read and write accesses with perpendicular magnetic tunnel junctions (p-MTJ) [1–2]. Furthermore, mature integration processes have been developed and 8Mb STT-MRAM with sub-5ns operation has shown high reliability [3]. Moreover, because of its non-volatility, STT-MRAM can reduce operation energy by more than 81% compared to SRAM for cache [1]. This paper presents STT-MRAM-based last level cache memory (LLC) including MRAM memory core, peripherals and cache logic circuits, using novel power optimization with high-speed power gating (HS-PG),considering processor architectures and cache memory accesses. The STT-MRAM-based cache has high reliability to reduce the write-error rate with novel write-verify-write. Furthermore, a read-modify-write scheme is implemented to reduce active power without penalty. Figure 7.2.1 presents a block diagram of a 4Mb STT-MRAM based cache.

We experimentally demonstrate a giant voltage-controlled magnetic anisotropy (VCMA) coefficient in a crystallographically strained CoFe layer (~15 monolayers in thickness) in a MgO/CoFe/Ir system. We observed a strong applied voltage dependence of saturation field and an asymmetric concave behavior with giant VCMA coefficients of −758 and 1043 fJ V−1 m−1. The result of structural analysis reveals epitaxial growth in MgO/CoFe/Ir layers and the orientation relationship MgO(001)[110] ∥ CoFe(001)[100] ∥ Ir(001)[110]. The CoFe layer has a bcc structure and a tetragonal distortion due to the lattice mismatch; therefore, the CoFe layer has a large perpendicular magnetic anisotropy.

This paper presents fast and low-power embedded nonvolatile memory technologies and circuit designs based on perpendicular STT-MRAM. Future prospects of applications are also discussed.

Nonvolatile memory, spin-transfer torque magnetoresistive RAM (STT-MRAM) is being developed to realize nonvolatile working memory because it provides high-speed accesses, high endurance, and CMOS-logic compatibility. Furthermore, programming current has been reduced drastically by developing the advanced perpendicular STT-MRAM [1]. Several-megabit STT-MRAM with sub-5ns operation is demonstrated in [2]. Advanced perpendicular STT-MRAM achieve ∼3× power saving by reducing leakage current in memory cells compared with SRAM for last level cache (LLC) [3]. Such high-speed RAM applications, however, entail several issues: the probability of read disturbance error increases and the active power of STT-MRAM must be decreased for higher access speed. Moreover, the leakage power of peripheral circuits must be decreased, because the high-speed RAM requires high-performance transistors having high leakage current in peripheral circuitry [4], limiting the energy efficiency of STT-MRAM. To resolve these issues, this paper presents STT-MRAM circuit designs: a short read-pulse generator with small overhead using hierarchical bitline for eliminating read disturbance, a charge-optimization scheme to avoid excessive active charging/discharging power, and ultra-fast power gating and power-on adaptive to RAM status for reducing leakage power.

This paper presents novel ultra-low power processor based on “Normally-off (N-off)” architecture, on which processors can remain in “off state” even during a short standby state. To realize “N-off” for high-performance (HP-) processors, we have developed novel STT-MRAM circuits and nonvolatile cache memories using them.

Since it has been difficult to increase clock frequency of processors due to power budget, there is a trend toward increase in number of processor cores and cache capacities (Fig. 1) to improve the processor performance. According to this trend, there have been two serious issues on the cache memories. One issue is large leakage power of SRAM-based cache (Ex. About 80% of average processor power in a mobile usage case [1]). Another one is large memory area of SRAM especially for last level cache (LLC) like L4 cache. Recently, eDRAM is used to reduce memory area for LLC (Fig. 1). However, gate length of eDRAM is difficult to be reduced less than 40–50 nm, and its power is not small due to frequent refresh (retention time ∼ 100µs.). To reduce the cache power and decrease memory area further at the same time, advanced STT-MRAM based cache has been considered promising from theoretical analysis [2]. However, both low power and high density LLC have not been ever clarified based on a realistic MTJ (magnetic tunneling junction) integration and circuit design. This paper presents solutions for the power and memory density with more advanced STT-MRAM cell technologies by low-temperature process development and novel cache memory architecture based circuit design.

A hybrid writing scheme that combines the spin Hall effect and voltage-controlled magnetic-anisotropy effect is investigated in Ta/CoFeB/MgO/CoFeB/Ru/CoFe/IrMn junctions. The write current and control voltage are applied to Ta and CoFeB/MgO/CoFeB junctions, respectively. The critical current density required for switching the magnetization in CoFeB was modulated 3.6-fold by changing the control voltage from −1.0 V to +1.0 V. This modulation of the write current density is explained by the change in the surface anisotropy of the free layer from 1.7 mJ/m2 to 1.6 mJ/m2, which is caused by the electric field applied to the junction. The read disturb rate and write error rate, which are important performance parameters for memory applications, are drastically improved, and no error was detected in 5 × 108 cycles by controlling read and write sequences.

This paper describes a scaling of MRAM cell area with advanced high performance CMOS technology. The cell area scalability for the cache memory considering MTJ resistivity, switching current, and drive current of access transistor are demonstrated. We consider the layout that the gate pitches are pinned at 3F to 4F. In order to minimize MRAM cell area, it indicates that MTJ resistivity and switching current are the most important factor. Novel scalability of memory cell size with CMOS technology node can be performed with advanced MTJ technology.

We evaluated embedded perpendicular spin transfer torque magnetic random access memory (STT-MRAM) performance fabricated by magnetic tunnel junction (MTJ) -“Last process”, which is able to expand material and structural design space of CMOS and MTJ, by SPICE simulation and test chip measurement. By the post-layout simulation, we show that the delay increase by parasitics, which originates from fabricating MTJ on the upper metal layer is below 50ps and negligible for most applications. And from the test chip measurement, we demonstrated switching operation as fast as 4ns, below 1V for STT-MRAM.

Magnetic RAM (MRAM) has a unique potential to change its memory capacity from small to large capacity. This paper presents a novel variable circuit based on 1T-1MTJ of perpendicular STT-MRAM memory arrays. It can cover all memory hierarchy and computing units that are variable and adjustable to applications by selecting single, dual or quadruple cell mode and changing circuit resources.

Circuit techniques for energy-efficient STT MRAM, which is suitable for replacing SRAM L2 cache memories, are proposed. The waking-up from the power-down mode without any cycle penalties becomes possible by eliminating the voltage generator even at higher frequency than 100MHz. The read current variation caused by the generator elimination is mitigated by 50% using the adaptive pulse-driven read current control. The cross-coupled hierarchical switch reduces the unneeded read current by 66% and enhances the read margin.

We demonstrated lower power consumption of mobile CPU by replacing high-performance (HP)-SRAMs with spin transfer torque (STT)-MRAMs using perpendicular (p)-MTJ. The key points that enable the low power consumption are adapting run time power gating architecture (shown in Fig. 1), and satisfying both fast and low-power writing, namely, 3 nsec and 0.09 pJ, of p-MTJ cell (shown in Fig. 3). As shown in Table 1, only our developed p-MTJ has achieved 3 nsec, 0.09 pJ. Thanks to the fast and low-power p-MTJ, the power consumption of cache memory could be reduced by over 80% without degradation of performance.

As the complementary metal oxide semiconductor (CMOS) scaling become harder, researchers have been trying to improve field programmable gate array (FPGA) performance by utilizing nonvolatile memory devices. This paper reports on a novel FPGA architecture where nonvolatile memory devices are used as nonvolatile reconfigurable switches (NRSs). It has found that resistive change memory (RCM) can be utilized as idealistic NRSs. To evaluate future performance of FPGA, we established evaluation method of interconnect circuit from international technology roadmap for semiconductor (ITRS) forecast. From FPGA scale evaluation, we show that there are two important design factor which affects overall FPGA performance, nonvolatile memory device characteristics and logic block cluster size. In terms of nonvolatile memory device characteristics, we have shown that the memory device whose resistivity of low resistance state (LRS) is around 10 kW gives superior performance by analysis of area and delay tradeoff. In terms of cluster size, larger cluster size is better for NRS-based FPGA since it can utilize small local programmable interconnect circuit composed of nonvolatile memory devices. From quantitative evaluation, area, delay and power of NRS-based FPGA can be improved by 25%, 24%, 29% compared to CMOS-based FPGA for 21 nm technology.

A new FPGA design using nonvolatile configuration memory (NCM) has been presented. NCM with large On/Off resistance ratio, such as nanoionic memory, is adopted to replace SRAM-based configuration memory. Since NCM is fabricated between interconnect layers of CMOS, silicon area is smaller than in the case of SRAM. Unlike previous FPGAs with nonvolatile programmable wires, we took architecture based approach for designing memory cell, since the cell area of programmable wire cell becomes larger than conventional SRAM-based configuration memory. We designed high-density NCM layout to evaluate the area reduction of configuration memory and verified the area of NCM is about 3.8X smaller than that of SRAM-based configuration memory, while it is 19X larger in the case of the programmable wire than SRAM-based one. It is expected that NCM achieved about over 20% reduction in total FPGA area. Area reduction of configuration memory also shortens the interconnect length to reduce the interconnect delay. Furthermore, nonvolatility achieves low power consumption with power gating.

In this paper, we present a novel nonvolatile-random access memory (RAM) cell design based on a “normally-off memory architecture” using a perpendicular spin torque transfer-magnetic random access memory (STT-MRAM) based on a four-transistors static random access memory (SRAM) in order to reduce the operating power of mobile processors. After the cell design concept and basic operation are proposed, a stable and reliable operation for read/write is confirmed by circuit simulation.

The scalability of a field programmable gate array (FPGA) using a spin metal-oxide-semiconductor field effect transistor (MOSFET) (spin FPGA) with a magnetocurrent (MC) ratio in the range of 100–1000% is discussed for the first time. The area and speed of million-gate spin FPGAs are numerically benchmarked with CMOS FPGA for 22, 32, and 45 nm technologies including a 20% transistor size variation. We show that the area is reduced and the speed is increased in spin FPGA due to the nonvolatile memory function of spin MOSFET.