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Prolyl-hydroxyproline (Pro-Hyp) levels increase in human blood on ingesting collagen hydrolysate and trigger proliferation of primary cultured fibroblasts attached on collagen. Such proliferative effects have been associated with the beneficial effects of collagen hydrolysate ingestion including enhancement of wound healing. However, some fibroblast cell lines do not respond to Pro-Hyp. In this study, we focused on the mesenchymal stem cell marker p75 neurotrophin receptor (p75NTR), because p75NTR-positive cells are increased at wound healing sites. Most fibroblasts that had migrated from the dissected mouse skin for 1–4 days expressed p75NTR. After prolonged cultivation, however, the ratio of p75NTR-positive fibroblasts dropped. The p75NTR-positive fibroblasts specifically incorporated fluorescein isothiocyanate (FITC)-labeled Pro-Hyp and Pro-Hyp significantly increased the number of p75NTR-positive fibroblasts grown on collagen gel. These results suggest that Pro-Hyp could enhance wound healing by stimulating p75NTR-positive fibroblasts at wound healing sites, while it has little effect on p75NTR-negative resident fibroblasts in normal tissues.

This paper explains indispensable “Key Words” to talk about future and J-DEVICES' approach.

In the photodecompositions of 4-methoxyphenyl azide (1) and 4-methylthiophenyl azide (5) in argon matrixes at cryogenic temperatures, benzazirine intermediates were identified on the basis of IR spectra. As expected, the benzazirines photochemically rearranged to the corresponding ketenimines and triplet nitrenes. Interestingly, with the methylthio substituent, the rearrangement of benzazirine 8 to ketenimine 7 occurred at 1.49 × 10(-5) s(-1) even in the dark at 10 K, despite a computed activation barrier of 3.4 kcal mol(-1). Because this rate is 10(57) times higher than that calculated for passing over the barrier and because it shows no temperature dependence, the rearrangement mechanism is interpreted in terms of heavy-atom tunneling.

具象物をAとし，巨視的概念（自然科学で使われる物質，金属，純物質，混合物，酸，塩基など）をBとする。BはAを包含するが，科学教育では，Bの理解は抽象的だから難しいといわれている。ここで「AならばBである」「AはBではない」などを「記述」とよぶ。本稿では，生徒・学生が一群の「記述」を学習して巨視的概念を形成する方法を明らかにする。授業実践における調査結果は，科学教育における「記述論理」の重要性を強く示唆している。, Let A be an "object" in the real world; and B be a macroscopic concept such as matter, metal, pure substance, mixture, acid, and base in natural science. A implies B, but it is well-known that understanding B is difficult in science education, because B is abstract. Here "A is B", "A is not B" etc are called "descriptions". The present paper deals with a method, by which a class of students learns a list of descriptions to form macroscopic concepts. The examination in an introductory science course suggests that "descriptive logic" plays a very important role in science education.

The concentration of agar and KCl in agar bridge may be respectively divided into three groups according to textbooks on chemical experiment. Preliminary experiment was done to examine the difference in the property of the agar bridge by the composition of the agar bridge as follows. Each of the solutions of CuSO4 and ZnSO4 in water was poured into the opposite side of agar bridge, which was prepared with various compositions in a test tube. Then the diffusion velocity of CuSO4 in agar bridge was measured. The obtained velocity in the lapse to time difference have showed a change with the composition of agar bridge. If KCl would have changed the structure of agar gel as well as sugar, the change of velocity by KCl concentration could be consistently explaned. But the one by agar concentration could not be explaned. As the effect of KCl upon the structure of agar gel has been in the stage of hypothesis, various experiments should been systematically done to explane the mechanism of the differencein the diffusion velocity of CuSO4.

A 4-way set associative TagRAM with 1.189-Mb capacity has been developed which can handle a secondary cache system of up to 16 Mbytes. A 9-ns cycle operation and clock to D/sub out/ of 4.7 ns are achieved by use of circuit techniques such as a pipelined decoding scheme, a single PMOS load BiCMOS main decoder, a BiCMOS sense-amplifying comparator, doubly placed self-timed write circuits, and highly linear VCO for a PLL. The device is successfully implemented with 0.7-/spl mu/m double polysilicon double-metal BiCMOS technology. >

A 64-kbyte snoopy cache memory was developed. The modified double word-line architecture with word-line buffers resulted in a large-size memory and a time-multiplex snoop operation by the pseudo-two-port method with a single-port cell. The flexible expandability was achieved by cascading multiple cache memories. The device was successfully implemented with 1.0- mu m double-polysilicon and double-metal CMOS technology. Low-power sense amplifiers and comparators limited power dissipation to 0.5 W at 40 MHz. >

A 32-kB cache macro with an experimental reduced instruction set computer (RISC) is realized. A pipelined cache access to realize a cycle time shorter than the cache access time is proposed. A double-word-line architecture combines single-port cells, dual-port cells, and CAM cells into a memory array to improve silicon area efficiency. The cache macro exhibits 9-ns typical clock-to-HIT delay as a result of several circuit techniques, such as a section word-line selector, a dual transfer gate, and 1.0- mu m CMOS technology. It supports multitask operation with logical addressing by a selective clear circuit. The RISC includes a double-word load/store instruction using a 64-b bus to fully utilize the on-chip cache macro. A test scheme allows measurement of the internal signal delay. The test device design is based on the unified design rules scalable through multigenerations of process technologies down to 0.8 mu m. >

A finely tunable standard cell (FTSC) method is introduced to cope with the complexity and high-speed nature of application-specific memory ICs (ASMICs). The method is applied to an integrated cache memory, a typical high-speed ASMIC, and achieves address-to-hit delay of 18 ns, which is comparable to that of a standard full-custom static RAM (SRAM). The FTSC offers the sizing capability of MOSFETs and stable delay elements composed of poly-Si resistors. >

A novel memory circuit, the transparent-refresh DRAM (TReD), is proposed to make a dynamic random-access memory (DRAM) virtually refresh-free, and a test device is successfully fabricated. The TReD uses dual-port dynamic RAM cells, one port of which is assigned for a refresh operation and the other port is assigned for a normal read/write operation. Using the configuration, users of the RAM are freed from a cumbersome refresh control without access-time degradation. The TReD cell size is about 1/2.5 of a 4-transistor SRAM (static RAM) cell, so that it can provide very-high-density RAM macros, which is functionally static. As a dual-port memory, the proposed dual-port DRAM cell size is 1/5 of the dual-port SRAM cell, and is suitable for large-scale dual-port memory macros in ASIC (application-specific integrated circuit) environments. >

A RISC CMOS superscalar microprocessor, operating at 75 MHz, executes up to four instructions per clock cycle, totalling 300M instructions per second. The chip implements a 64 b architecture and includes a 64 b integer pipeline, 16 kB instruction cache (Icache), 16 kB data cache (Dcache), 1 k entries of branch cache (Bcache) for branch prediction and a 384 entry translation lookaside buffer (TLB). The chip has a separate floating-point unit (FPU) with maximum performance of 300MFLOPS. The FPU is fed by two 64 b-wide banks of external cache configurable from one to 16 MB. The chip set has a mechanism for treating 32 b operation as a subset of the 64 b architecture and supports multi-processing. The chip is fabricated in 0.5 /spl mu/m CMOS with triple layer metal, double poly Si for high density cache and triple-well. The die is 17.34/spl times/17.30 mm/sup 2/ and includes 2.6 M transistors. The package is a 59 1-pin CPGA with 382 signal pins. Power dissipation is 13 W from a 3.3 V supply at 75 MHz. >

Design of embedded memories for a 64 bit superscaler RISC microprocessor is described. Since the microprocessor issues four instructions per cycle including two memory operations at a time, very wide bandwidth of the primary caches (2.4 GB/sec) is vital. The chip includes 16 KB instruction cache, 2 KB branch cache, 16 KB dual ported data cache and 384 entry dual ported TLB. Unique scheme of TLB hit check greatly reduces critical path. The chip is fabricated in Toshiba's high-speed 0.8 /spl mu/m CMOS technology utilizing triple metal and triple well. The die size is 17.3 mm/spl times/17.3 mm and contains 2.6 million transistors. The chip achieves 75 MHz at 70/spl deg/C and 3.1 V. >

The authors describe an on-chip cache/TLB macro which can be integrated with highly concurrent RISC (reduced instruction set computer) processors. The macro incorporates TLB, a 16-kbyte instruction cache, and a 16-kbyte two-port data cache. It executes virtual-to-physical address translation and following physical cache access in 12 ns. The total bandwidth is 2.6 Gbyte/s at 80 MHz. A test chip was fabricated with 0.5- mu m double-polysilicon triple-metal CMOS technology. >

An SRAM that has column-sliceable peripheral circuitry embedded in a 235 K CMOS gate array and improved flexibility in configuration is described. The port-configurable (PC) SRAM cell achieves the minimum area overhead associated with the configurability by using four port-customization terminals at every memory-cell boundary. Prior to customization, first and second polysilicon are used to connect the internal memory-cell nodes to the port-customization terminals. Multiport SRAMs are configured by first Al so that corresponding internal nodes of adjacent memory cells are connected. At the same time, word lines are configured according to the port customization using second Al and the via hole. The use of second Al is a key to the density and speed. A high-resistance polysilicon load cell is used to provide good write operation and high density. The cell size is 9*13.6 mu m, one-tenth the area of an equivalent multiport cell based on gate-array basic cells. The worst-case access speed of multiport configuration based on this scheme has no dependence on the number of ports because the memory-cell current available to drive unit bit-line load capacitance remains constant. In the multiport configuration, the write operation from one port must flip all of the connecting cells through the NMOS transfer gate of the write port cell. Therefore, a six-transistor full CMOS SRAM cell is not suitable for PC SRAM. >

The 1-Mb RAM utilizes a one-transistor, one-capacitor dynamic memory cell. Since all the refresh-related operations are done on chip, the RAM acts as a virtually static RAM (VSRAM). The refresh operations are merged into the normal operation, called a background refresh, the main feature of the VSRAM. Since the fast operation of the core part of the RAM is crucial to minimize the access-time overhead by the background refresh, 16 divided bit lines and parallel processing techniques are utilized. Novel hot-carrier resistant circuits are applied selectively to bootstrapped nodes for high hot-carrier reliability. N-channel memory cells are embedded in a p-well, which gives a low soft error rate of less than 10 FIT. 1-/spl mu/m NMOSFETs with moderately lightly doped drain structures offer fast 5-V operation with sufficient reliability. An advanced double-level poly-Si and double-level Al twin-well CMOS technology is developed for fast circuit speed and high packing density. The memory cell size is 3.5/spl times/8.4 /spl mu/m/SUP 2/, and the chip size is 5.99/spl times/13.8 mm./SUP 2/. Address access time is typically 62 ns, with 21-mA operating current and 30-/spl mu/A standby current at room temperature.

The system, circuit, layout and device levels of an integrated cache memory (ICM), which includes 32 kbyte DATA memory with typical address to HIT delay of 18 ns and address to DATA delay of 23 ns, are described. The ICM offers the largest memory size and the fastest speed ever reported in a cache memory. The device integrates a 32 kbyte DATA INSTRUCTION memory, a 34 kbit TAG memory, an 8 kbit VALID flat, a 2 kbit least recently used (LRU) flag, comparators, and CPU interface logic circuits on a chip. The inclusion of the DATA memory is crucial in improving system cycle time. The device uses several novel circuit design technologies, including a double-word-line scheme, low-noise flush clear, a low-power comparator, noise immunity, and directly testable memory design. Its newly proposed way-slice architecture increases both flexibility and expandability. >

A 1-Mb (128K*8) pseudostatic RAM (PSRAM) is described. A novel feature of the RAM is the inclusion of a virtually static RAM (VSRAM) mode, while being fully compatible with a standard PSRAM. The RAM changes into the VSRAM mode when the RFSH pin is grounded, even in active cycles. The RAM can be used either as a fast PSRAM of 36-ns access time or as a convenient VSRAM of 66-ns access time. The typical operation current and data-retention current are 30 mA at 160-ns cycle time and 30 mu A, respectively. In order to achieve high-speed operation, low data-retention current, and high reliability, the RAM uses delay-time tunable design, a current-mirror timer, hot-carrier resistant circuits, and an optimized arbiter. These technologies are applicable to general advanced VLSIs. >

The phase transition point of solid hexabromoethane was found at 177°C, above which the crystal is a body centered cubic lattice with two molecules in a unit cell, having a cell length of 7.80 A at 185°C. From an analysis of entropy change, it seems that random orientations of the molecular axis would occur at the transition point. The influence of halogen substitution is discussed. It was concluded that the phase transition will be dominated mainly by the geometrical properties of the molecules.

The architectural aspects of a newly deveoped integrated cache memory is described in this paper, which includes 32Kbyte DATA memory with a typical ADDRESS to HIT delay, the largest memory size and fastest speed ever reported as an integrated cache memory[1]. The device integrates data/instruction memory, tag memory and a comparator on a chip. It serves as a cache memory of several host MPUs by aluminum masterslice.

A 46ns 32K×8 CMOS RAM fabricated with double metal, double poly 1.2μm P-well technology will be reported. The RAM(59.2mm2) has a 10mW operating power at 1MHz and a 30μW standby power.

The phase transition point of solid hexabromoethane was found at 177°C, above which the crystal is a body centered cubic lattice with two molecules in a unit cell, having a cell length of 7.80 A at 185°C. From an analysis of entropy change, it seems that random orientations of the molecular axis would occur at the transition point. The influence of halogen substitution is discussed. It was concluded that the phase transition will be dominated mainly by the geometrical properties of the molecules.

A 1-Mb DRAM (dynamic random-access memory) is embedded in a 72-K-raw-gates channelless gate array fabricated in 1.0- mu m HC/sup 2/MOS twin-well technology. The DRAM design is optimized for embedding, such as the adaptation of no substrated bias design and p-well protected n-channel memory cells. The typical delay time of the gate array is 0.4 ns, and the worst-case access time of the DRAM is 60 ns. >