25 results on '"Kawanaka, Shigeru"'
Search Results
2. A high performance pMOSFET with two-step recessed SiGe-S/D structure for 32 nm node and beyond
3. Analysis on high-frequency characteristics of SOI lateral BJTs with self-aligned external base for 2-GHz RF applications
4. A novel lateral bipolar transistor with 67 GHz fmax on thin-film SOI for RF analog applications
5. Simulation of planar single-gate Si tunnel FET with average subthreshold swing of less than 60 mV/decade for 0.3 V operation
6. Implementation of TFET SPICE Model for Ultra-Low Power Circuit Analysis
7. Novel VTH self-adjusting MISFET with SiN charge trap layer for ultra low power LSI
8. Mechanism of Contact Resistance Reduction in Nickel Silicide Films by Pt Incorporation
9. (Invited) Quantitative Correlation Between Low-Field Mobility and High-Field Carrier Velocity in Quasi-Ballistic-Transport MISFETs with High-k Gate Dielectrics
10. Palladium incorporated nickel silicide for a cost effective alternative salicide technology for scaled CMOS
11. A study on aggressive proximity of embedded SiGe with comprehensive source drain extension engineering for 32nm node high-performance pMOSFET technology
12. Dual nature of metal gate electrode effects on BTI and dielectric breakdown in TaC/HfSiON MISFETs
13. In situDoped Embedded-SiGe Source/Drain Technique for 32 nm Node p-Channel Metal–Oxide–Semiconductor Field-Effect Transistor
14. Clarification of Additional Mobility Components associated with TaC and TiN Metal Gates in scaled HfSiON MOSFETs down to sub-1.0nm EOT
15. A high performance pMOSFET with two-step recessed SiGe-S/D structure for 32nm node and beyond
16. Threshold Voltage Control of Hf-based High-κ Gate Stack System by Fluorine Incorporation into Channel and Its Impact on Short-Channel Characteristics
17. Advanced CMOS Technology beyond 45nm Node
18. HfSiON gate dielectric technology for CMOSFET application
19. Double Gate MOSFET by ESS (Empty Space in Silicon) Architecture
20. Advantages of SOI technology in low-voltage ULSIs
21. 25-nm Gate Length nMOSFET With Steep Channel Profiles Utilizing Carbon-Doped Silicon Layers (A P-Type Dopant Confinement Layer).
22. Advantages of SOI technology in low-voltage ULSIs.
23. Novel VTH self-adjusting MISFET with SiN charge trap layer for ultra low power LSI.
24. In situ Doped Embedded-SiGe Source/Drain Technique for 32 nm Node p-Channel Metal–Oxide–Semiconductor Field-Effect Transistor.
25. (Invited) Quantitative Correlation Between Low-Field Mobility and High-Field Carrier Velocity in Quasi-Ballistic-Transport MISFETs with High-kGate Dielectrics
Catalog
Books, media, physical & digital resources
Discovery Service for Jio Institute Digital Library
For full access to our library's resources, please sign in.